FLEX-IMX8M-Mini HARDWARE MANUAL
– VER 1.00 – JAN 31 2020
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5.2. MIPI Display
The Mobile Industry Processor Interface (MIPI) Display Serial Interface (DSI) controller is a flexible,
high-performance, and easy-to-use digital core that implements all protocol functions defined in the
MIPI DSI Specification. The MIPI DSI controller provides an interface that allows communication with
MIPI DSI-compliant peripherals. The MIPI DSI D-PHY is a high frequency, low power, low-cost,
source-synchronous, physical layer supporting the MIPI Alliance standard for D-PHY.
Key features of the MIPI DSI Controller Core include:
•
Implements all three DSI Layers (Pixel to Byte packing, Low Level Protocol, Lane
Management)
•
Support for Command and Video Modes
•
Host Version
•
Scalable data lane support, 1 to 4 Data Lanes
•
Optional bidirectional support on lane 0
•
Supports High Speed and Low Power operation
•
Support for all DSI data types and formats
•
Virtual Channel support
•
Supports ULPS mode
•
Full Low-Level Protocol Error and Contention detection and reporting
•
Supports continuous and non-continuous Clock Lane operation
•
Supports multiple packets per transmission
•
Support for all three Video Mode packet sequences
•
Non-Burst Mode with Sync Pulses
•
Non-Burst Mode with Sync Events
•
Burst mode
•
Support for bus turnaround signaling
•
Flexible packet based user interface
•
APB interface option (status and control)
•
Display Pixel Interface Core (DPI-2) option
•
Display Bus Interface Core (DBI-2) option
•
Supports PHY Protocol Interface (PPI) compatible MIPI D-PHYs
•
MIPI Alliance Specification for Display Serial Interface Version 1.1 compliant
For additional details
, please refer to the “MIPI DSI Host Controller (MIPI_DSI)” chapter of the
“i.MX8M Mini Applications Processor Reference Manual”.
