EDM1-IMX6 HARDWARE MANUAL
– VER 1.00 – NOV 14 2019
Page
42
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3.6. PCI Express
The EDM1-IMX6 is equipped with a single lane PCI Express interface, implemented in the i.MX6
processor.
The PCI Express interface complies with PCIe specification Gen 2.0 and supports the PCI Express
1.1/2.0 standards. The PCI Express module is a dual mode complex, supporting root complex operations
and endpoint operations.
PCI Express PHY Features
•
5 Gbps data transmission rate
•
Integrated PHY includes transmitter, receiver, PLL, digital core, and ESD.
•
Programmable RX equalization
•
Designed for excellent performance margin and receiver sensitivity
•
Robust PHY architecture tolerates wide process, voltage and temperature variations
•
Low-jitter PLL technology with excellent supply isolation
•
IEEE 1149.6 (JTAG) boundary scan
•
Built-in Self-Test (BIST) features for production, at-speed, testing on any digital tester
•
5Gb/s PCIe Gen 2 and 2.5Gb/s PCIe Gen 1.1 test modes supported
•
Advanced built-in diagnostics including on-chip sampling scope for easy debug
•
Visibility & controllability of hard macro functionality thru programmable registers in the design
•
Over-rides on all ASIC side inputs for easy debug
•
Access register space thru simple 16 bit parallel interface
•
Access register space thru JTAG
For additional details, please refer to the “PCI Express (PCIe)” chapter of the “i.MX6 Reference Manual”.
Table 18 - PCI Express Signal Description
EDM
PIN
i.MX6
BALL
PAD NAME
Signal
V
I/O
Description
85
D7
CLK1_P
XTALOSC_CLK1_P
2V5
O
PCI Express channel A clock
differential pair positive signal
87
C7
CLK1_N
XTALOSC_CLK1_N
2V5
O
PCI Express channel A clock
differential pair negative
signal
91
B3
PCIE_TXP
PCIE_TX_P
2V5
O
PCI Express channel A
Transmit output differential
pair positive signal
93
A3
PCIE_TXM
PCIE_TX_N
2V5
O
PCI Express channel A
Transmit output differential
pair negative signal
97
B2
PCIE_RXP
PCIE_RX_P
2V5
I
PCI Express channel A
Receive input differential pair
positive signal
99
B1
PCIE_RXM
PCIE_RX_N
2V5
I
PCI Express channel A
Receive input differential pair
negative signal
119
H21
EIM_D31
GPIO3_IO31
3V3
O
PCI Express Reset signal for
external devices
NOTE: The PCIE_RX pair has decoupling capacitors on the EDM module valued 10nF
