EDM1-IMX6 HARDWARE MANUAL
– VER 1.00 – NOV 14 2019
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2.1.1. i.MX6 Memory Interfaces
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The memory system consists of the following components:
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Level 1 Cache
—32 KB Instruction, 32 KB Data cache per core
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Level 2 Cache
—Unified instruction and data (1 MByte)
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On-Chip Memory:
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Boot ROM, including HAB (96 KB)
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Internal multimedia / shared, fast access RAM (OCRAM, 256 KB)
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Secure/non-secure RAM (16 KB)
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External memory interfaces:
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16-bit, 32-bit, and 64-bit DDR3-1066 and LV-DDR3-1066
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8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size,
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BA-NAND, PBA-NAND, LBA-
NAND, OneNAND™ and others. BCH ECC up to 32 bit.
2.1.2. i.MX6 DMA Engine
The SDMA is multi-channel flexible DMA engine. It helps in maximizing system performance by off-
loading the various cores in dynamic data routing. It has the following features:
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Powered by a 16-bit Instruction-Set micro-RISC engine
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Multi-channel DMA supporting up to 32 time-division multiplexed DMA channels
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48 events with total flexibility to trigger any combination of channels
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Memory accesses including linear, FIFO, and 2D addressing
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Shared peripherals between ARM and SDMA
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Very fast Context-Switching with 2-level priority based preemptive multi-tasking
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DMA units with auto-flush and prefetch capability
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Flexible address management for DMA transfers (increment, decrement, and no address
changes on source and destination address)
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DMA ports can handle unit-directional and bi-directional flows (copy mode)
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Up to 8-word buffer for configurable burst transfers
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Support of byte-swapping and CRC calculations
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Library of Scripts and API is available
