Tandy 6000 HD, Руководство по обслуживанию

Страница: 86 / 416

Table 7-3 outlines the memory map of the MC68000 subsystem:
Service Manual TANDY 6000/6000-HD
---------------------------------------------------------------------- TAN D Y COMPUTER PRODUCTS --------------------------------------------------------------------
SYSTEM RAM
Table 7-3. Memory Map of the MC68000 Subsystem
7.2.8 Clock Logic
The clock logic provides the clocks and timing for the
MC68000 subsystem. The heart of the clock logic is a 48 MHz
crystal oscillator (Yl). See the top left-hand corner of
sheet 2 of the MC68000 CPU schematic. The 48 MHz output of
Yl is buffered by 1/4 of U47 which is input to the clock
inputs of U46 (F161) and U53 (F175). U46 is a 4 bit
synchronous counter and is used to divide the 48 MHz input
into 4 output clocks. The counter is preloaded with a count
of 9 or 1 depending on the state of QD output (U46 pin 11).
the counter will count to X110 and preload again. This
generates a divide by 2 at U46 pin 14 (24 MHz), a divide by
4 at pin 13 (non symmetrical 12 MHz), a divide by 6 at pin
12 (8MHz), and a divide by 12 at pin 11 (4MHz). The 24 MHz
output is divided by 2 by 1/4 of U52 (F86) and U53 (F175).
the 8 and 4 MHz outputs are also clocked through U53 to
assure all three clocks are synchronous with each other.
- 82 -
Start Address
End Address Total Bytes
Total Available RAM Space in Supervise Mode
000000
6FFFFF 7 MEG
Total Available Protected RAM Space in User Mode
000000
o f f f f f
1 MEG
One 128K Memorv Board Installed
000000 01FFFF 128K
Two 128K (or one 256K) Memory Boards Installed
000000 03FFFF
256K
One 256K and One 128K Memory Board Installed
000000 05FFFF 384K
Two 256K Memory Boards or One 512K Memory Board Installed
000000 07FFFF 512K
Three 256K Memory Boards Installed or One 512K and One 256K
Memory Board Installed
000000 09FFFF 768K
One 1 MEG Memory Board Installed
000000
o f f f f f
1 MEG