Tandy 6000 HD, Руководство по обслуживанию

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Service Manual
TANDY 6000/6000-HD
TAN D Y COMPUTER PRODUCTS ----------------------------------------------------------------------
is displayed "not in pieces" but as a single entity. After
the eight dot scans are output, the electron beam is turned
off and two rows (the 9th and 10th) of blank dots are
output. This provides separation between character lines.
Once these two rows are output, the system is ready to
output the first row of the second character line.
Following the path the data goes through before being output
at pin 9 of UlO (Vout), the Vout signal is delayed quite a
bit with respect to the Display Enable and Cursor signals.
For this reason, the two signals are delayed by two TADCLK
cycles and Reverse Video (REVID) is delayed by one TADCLK
cycle with respect to the Vout signal. This is shown by
U12. Note how the delayed cursor and DREVID are exclusive
ORed (U4 pins 12 and 13). The resulting signal at pin 11 of
U4 is also exclusive ORed with Vout (U4 pins 9 and 10).
Either the cursor, the Reverse Video or the Video will be
displayed in a character location, but not two of them at
the same time. The signal output at pin 8 of U4 is finally
enabled by the Display enable and either one of the RCLOCK,
RCLOCK*, RCLOCKP, or RCLOCKP* signals. One of these signals
is chosen to achieve the best result. The final signal at
pin 12 of U15 is simply called VIDEO. The VIDEO, HSYNC, and
VSYNC signals are separately shielded and sent to the CRT
Logic board (ground signals are wrapped around them).
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