Tandy 6000 HD, Руководство по обслуживанию

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Service Manual
TANDY 6000/6000-HD
TANDY COMPUTER PRODUCTS ------------------------------------------------------------------------
The Reset (RES*) input is used to reset the CRTC. It is an
active low. When this signal is active, the CRTC is forced
into the following status:
All the counters in CRTC are cleared and the device
stops the display operation.
All the outputs go to a low level.
The control registers of the CRTC are not affected.
Display Refresh
The CRTC internal register file is programmed to display
either a 80 x 24 or 40 x 24 alphanumeric character format.
The address of each of these characters is stored in the
display memory. That is why only 2K of Video RAM is
required (just enough to store the entire screen density).
Everything that is displayed on the screen must be refreshed
continuously or it will fade and disappear. Each character
is a dot matrix of 8 x 10 cells and every cell is refreshed
approximately 60 times a second. The CRT beam scans the
screen from top to bottom, refreshing every dot whose
location is indicated by the coordinates that the display
memory and the character ROM receive from the CRTC (memory
refresh address and Row address).
The CRTC takes care of this particular chore while the CPU
takes care of other more important tasks. However, every
time the CPU^addresses its upper 2K bytes of memory, it
automatically takes control of the Video RAM. The reason is
that these 2K bytes, locations F800H through FFFFH, overlap
the video memory in its entirety. Thus the display RAM can
be accessed by either the CPU or the CRTC, but not by both
at the same time.
The processor (CPU) gets priority access anytime, but is
synchronized by an interrupt to perform accesses only during
the vertical retrace time. The vertical retrace time is
defined as the time it takes the CRT beam to return from the
end of the very last scan line back to the start of the very
first one. The CRT beam is shut off during the retrace
time.
The CRTC sends its addresses as follows: The first set of
address lines, consisting of MAO through M A 1 0 , cycles
binarily through the display memory and is incremented with
each clock pulse (CCLK), one per character displayed. The
second set (RA0-RA4) addresses the row-address select lines
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