Tandy 6000 HD, Руководство по обслуживанию

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Service Manual
TANDY 6000/6000-HD
TAN D Y COMPUTER PRODUCTS ----------------------------------------------------------------------
The waveform at pin 8 of Ul resembles a "raw" square wave
with a frequency of approximately 12.48 MHz.
At pin 2 of the same chip, the signal appears more like a
"clean" square wave. It is labeled RCLOCK and is fed
through inverter Ul pin 13 and exits pin 12 as RCLOCK*. The
asterisk indicates that the signal is an active low, i.e. if
RCLOCK is normally an active high, RCLOCK* will be an
active low.
At pin 3 of Ul, RCLOCK* goes through an inverter to give
RCLOCKP (RCLOCK prime) and through a second inverter to
yield RCLOCKP*. Up to this point, all clock pulses have the
same frequency (12.48 MHz) but different phases.
All these different clock pulses are generated to provide
the timing to synchronize the various activities of the
video system. Some activities should take place before
others while some should occur three or four times as often
as others. RCLOCK is divided by 2 by a D Flip-Flop, pins 3
and 5 of U17. This provides a frequency of 6.24 MHz, which
is then NANDed with the 80*/40 character Enable. When this
signal is low (active), 80 characters per line will be
displayed on the screen. When the signal is high, only 40
characters will appear on the screen.
CLOCK (at pin 6 of U28, test point T P 2 6 ) is either 12.48 MHz
(for 80 characters) or 6.24 MHz (for 40 characters). Note
that the NAND gate (U28 pins 1, 2, and 3) is used here as an
inverter. CLOCK goes through inverter U33 (pins 1 and 2) to
become D C L K , which is the DOT CLOCK. Its frequency (either
6.24 or 12.48 MHz) is the rate at which video information is
shifted to the CRT.
CLOCK, which is a phase-shifted DOT CLOCK, is divided by the
4-bit counter (U26) to produce the character-rate clock
labeled as CCLK with a frequency of 1.56 MHz (for 80
characters) or 0.78 MHz (for 40 characters). This 4-bit
counter (LS163) is synchronous (all its flip-flops are
clocked simultaneously) so that the outputs change
coincident with each other when instructed by the
count-enable inputs and internal gating. The DOT CLOCK
triggers the four flip-flops on the rising edge of its wave
form. The count is accomplished as follows (in HEX): 0, 9,
A, B, C, D, E, F, 0, 9, A, B, C,...etc. This is best
described by the timing diagram in Figure 7-11. Notice that
both 40 and 80 character modes are represented here and that
the signals TCLK* and PLCLK* are also shown on this diagram.
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