Tait TB7100, Инструкция по установке и эксплуатации

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28 Functional Description TB7100 Installation and Operation Manual
© Tait Electronics Limited December 2005
RF PLL
The RF PLL consists of the following:
■
RF PLL device
■
loop filter
■
VCO (voltage-controlled oscillator)
■
VCO output switch
The RF PLL has fast-locking capability but coarse frequency resolution.
The above combination of control loops creates improved frequency
generation and acquisition capabilities.
Operation of
Control Loop
The RF PLL is a conventional integer-N design with frequency resolution
of 25kHz. In transmit mode the loop locks to the transmit frequency.
Initially, the VCO generates an unregulated frequency in the required range.
This is fed to the PLL device (ADF4111) and divided down by a
programmed ratio to approximately 25 kHz. The reference frequency input
from the FCL is also divided down to approximately 25 kHz. The phase of
the two signals is compared and the error translated into a DC voltage by a
programmable charge pump and dual-bandwidth loop filter. This DC signal
is used to control the VCO frequency and reduce the initial error. The loop
eventually settles to a point that minimises the phase error between divided-
down reference and VCO frequencies. The net result is that the loop locks
to a programmed multiple of the reference frequency.
The FCL generates an output of 13.012± 0.004 MHz. Initially a VCXO
produces a quasi-regulated frequency in the required range. The VCXO
output is fed to a mixer where it is mixed with the 13.000 MHz TCXO
frequency. The mixer, after low-pass filtering to remove unwanted products,
produces a nominal frequency of 12 kHz. This is converted to digital form
and transported to the frequency-control block in custom logic.
The frequency-control block compares the mixer output frequency with a
reference generated by the digital clock and creates a DC error signal. A
programmed offset is also added. This error signal is converted to analog
form and used to control the VCXO frequency and reduce the initial error.
Once settled, the loop locks to the TCXO frequency with a programmed
offset frequency. The FCL output therefore acquires the TCXO’s frequency
stability.
Modulation
The full bandwidth modulation signal is obtained from the DSP in digital
form at a sample rate of 48kHz. In traditional dual-point modulation
systems the modulation is applied, in analog form, to both the frequency
reference and the VCO in the RF PLL, combining to produce a flat
modulation response down to DC. Reference modulation is usually applied
directly to the TCXO.