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14
USB 2.0 (USB20SR) Device IP Core User Guide
System Level Solutions
January 2013
Core Registers
1. Endpoint buffer memory (2K size) is starting from offset address
0X20000.
2. The above table includes all 15 endpoint register details of the IP Core
with its offset. From these endpoint registers, only those are applicable
whose support is enabled inside the hardware. For example if IP Core
supports 6 endpoints then all endpoints from 0 to 5 are applicable while
endpoints from 6 to 15 are not applicable. The IP Core supports 3
endpoints by default.
DCVERSION
This register represent IP Core Version/Product ID description of the core. .
Table 4-2 shows the DCVERSION register description.
Value after Reset : 00000000h
70 EP14_CSR 0x120 32 RW EndPoint 14 CSR Register
71 EP14_IMS 0x124 32 ROC EndPoint 14 Interrupt Register
72 EP14_BUFFER0 0x128 32 RW EndPoint 14 Buffer0 Register
73 EP14_BUFFER1 0x12c 32 RW EndPoint 14 Buffer1 Register
74 EP15_CSR 0x130 32 RW EndPoint 15 CSR Register
75 EP15_IMS 0x134 32 ROC EndPoint 15 Interrupt Register
76 EP15_BUFFER0 0x138 32 RW EndPoint 15 Buffer0 Register
77 EP15_BUFFER1 0x13c 32 RW EndPoint 15 Buffer1 Register
Table 4-1. Register Description
Sr.
No.
Register Offset Width Access Description
Table 4-2. DCVERSION Register Details
Bit Access Description
31:16 RO These bits represent the hexadecimal value of Product ID. (i.e. 0A04 for USB20SR)
15:8 RO These bits represent the hexadecimal value of IP Core Version. (i.e. 13 for IP Core Ver-
sion 1.3)
7:0 RO These bits represent the hexadecimal value of Customer Number and Customer
Release Number. (i.e. 0 for Customer Number and 0 for Customer Release Number, if
any)