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USB 2.0 (USB20SR) Device IP Core User Guide
System Level Solutions
January 2013
4. Core Registers
This section describes all the registers inside the USB20SR Core. The
Register field describes the name of the register. The Offset field describes
the offset of register in USB IP. The Access field describes the type of access
to the register that is read or write. Description field describes the type and
function of register. Table 4-1 shows the register details.
Table 4-1. Register Description
Sr.
No.
Register Offset Width Access Description
1 DCVERSION 0x00 32 RO IP Core Version/Product ID description register
2 FUNC_ADR 0x04 8 RW USB function address register
3 INT_MSK 0x08 16 RW Interrupt Mask for endpoint independent interrupt
sources
4 INT_SRC 0x0c 32 ROC Interrupt source register
5 MAIN_CSR 0x10 8 RW Control/Status register
6 FRM_NAT 0x14 32 RO Frame number and time
7 TEST_MODE 0x20 8 RW Test mode register for enabling test mode inside
the IP Core
8 SETUP_PACK_1 0x30 32 RO First four bytes of received setup packet
9 SETUP_PACK_2 0x34 32 RO Second four bytes of received setup packet
10 ULPI_PHY_CS 0x1f0 8 RW ULPI PHY Chip enable or disable register
11 ULPI_REG_
ACCESS
0x1f4 32 RW ULPI PHY Chip register read/write register
12 D_SPEED_SEL 0x1f8 8 RW Device IP Core speed select register
13 D_CNCT 0x1fc 8 RW Device Connect/Disconnect register
14 EP0_CSR 0x40 32 RW EndPoint 0 (Control Endpoint): CSR Register
15 EP0_IMS 0x44 32 ROC EndPoint 0 (Control Endpoint): Interrupt Register
16 EP0_BUFFER0 0x48 32 RW EndPoint 0 (Control Endpoint): Buffer0 Register