Supero X7DCT-3, Руководство пользователя

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X7DCT-L/X7DCT-3/X7DCT-IBX/X7DCT-3IBX User's Manual
Enable Master
This setting allows you to enable the selected device as the PCI bus master.
The options are Enabled and Disabled .
Latency Timer
This setting allows you to set the clock rate for the Bus Master. A high-priority,
high-throughout device may benefi t from a greater clock rate. The options are
Default , 0020h, 0040h, 0060h, 0080h, 00A0h, 00C0h, and 00E0h. For Unix,
Novell and other Operating Systems, please select the option: Other. If a drive
fails after a new software is installed, you might want to change this setting and
try again. A different OS requires a different Bus Master clock rate .
Large Disk Access Mode
This setting defi nes the area in a hard drive that can be accessed by the user.
The options are DOS or Other (for Unix, Novelle NetWare and other operating
systems).
X
Advanced Chipset Control
Access the submenu to make changes to the following settings.
Warning
: Take caution when changing the Advanced settings. An Incor-
rect value, timing or a very high DRAM frequency may cause system
instability. When this occurs, reset the setting to the default setting.
Accelerate MRC
Select Disable to skip Memory Reference Code (MRC) processing at bootup if there
is no change to DIMM population. The options are Enabled and Disabled .
Clock Spectrum Feature
If Enabled, the BIOS will monitor the level of Electromagnetic Interference caused
by the components and will attempt to decrease the interference whenever needed.
The options are Enabled and Disabled .
Crystal Beach Confi guration Enable
Select Enabled to use the Intel I/O AT (Acceleration Technology) to accelerate the
performance of TOE devices. ( Note : A TOE device is a specialized, dedicated pro-
cessor installed on an add-on card or a network card to handle some or all packet
processing of this add-on card. For this motherboard, the TOE device is built inside
the Intel ICH9 South Bridge chip.) The options are Enabled and Disabled.
SERR Signal Condition
This setting specifi es the ECC Error conditions that an SERR# is to be asserted.
The options are None, Single Bit , Multiple Bit, and Both.