Supero X7DCT-3, Руководство пользователя

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Chapter 1: Introduction
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1-2 Chipset and Processor Features Overview
Built upon the functionality and the capability of the Intel 5100 chipset, the X7DCT-L/
X7DCT-LF/X7DCT-3/X7DCT-3F/X7DCT-3IBXF motherboard provides the per-
formance and feature set required for dual processor-based high-end computer
systems with confi guration options optimized for intensive computing, high energy-
effi ciency and High-performance computing (HPC) applications. The 5100 chipset
supports single or dual Intel Xeon 64-bit Dual-Core 5400/5300/5200/5100 Series
processors with front side bus speeds of up to 1.333 GHz. The chipset consists
of the 5100 Memory Controller Hub (MCH), Intel I/O Controller Hub (ICH9R) and
the I/O subsystem.
The 5100 Memory Controller Hub (MCH)
The Intel 5100 MCH chip is designed for symmetric multiprocessing across two
independent front side bus interfaces. Each front side bus uses a 64-bit wide,
1333/1066 MTS data bus capable of transferring data at 10.6/8.5 GB/s for a total
bandwidth of 17/21.3 GB/s. The MCH supports a 36-bit wide address bus and up to
six DDR2 667 MHz/533 MHz Registered DIMM modules, providing a total memory
capacity of up to 48 GB.
The 5100 MCH also provides one x16 interfaces and one x4 DMI Interface to the
ICH9R. Each PCI Express port on the MCH provides 4 GB/s bi-directional band-
width.
The Ninth Generation I/O Controller Hub (ICH9R)
The I/O Controller ICH9R provides the data buffering and interface arbitration re-
quired for the system to operate effi ciently. It also provides the bandwidth needed
for the system to maintain its peak performance. The Direct Media Interface (DMI)
provides the connection between the MCH and the ICH9R. The ICH9R supports up
to three PCI-Express x1 connections, one PCI connection, four Serial ATA ports and
fi ve USB 2.0 ports. In addition, the ICH9R offers the Intel Matrix Storage Technology
which provides various RAID options for data protection and rapid data access. It
also supports next generation of client management through the use of PROActive
technology in conjunction with Intel's next generation Gigabit Ethernet controllers.