2-28
X6DAL-XTG User's Manual
IDE Connectors
The IDE Connectors are lo-
cated on J44 (IDE1) and J38
(IDE 2), You do not need to
configure jumpers for these
connectors. See the table
on the right for pin defini-
tions.
Pin Number
Function
1
Reset IDE
3
Host Data 7
5
Host Data 6
7
Host Data 5
9
Host Data 4
11
Host Data 3
13
Host Data 2
15
Host Data 1
17
Host Data 0
19
GND
21
DRQ3
23
I/O W rite-
25
I/O Read-
27
IOCHRDY
29
DACK3-
31
IRQ14
33
Addr 1
35
Addr 0
37
Chip Select 0
39
Activity
Pin Number
Function
2
GND
4
Host Data 8
6
Host Data 9
8
Host Data 10
10
Host Data 11
12
Host Data 12
14
Host Data 13
16
Host Data 14
18
Host Data 15
20
Key
22
GND
24
GND
26
GND
28
BALE
30
GND
32
IOCS16-
34
GND
36
Addr 2
38
Chip Select 1-
40
GND
IDE Connector Pin Definitions
(J44, J38)
KB/
Mouse
DIMM 3A
DIMM 3B
DIMM 2A
DIMM 2B
DIMM 1A
DIMM 1B
Tumwater
(North Bridge)
Marvell
IDE #1
IDE #2
U
SB
0/1
COM2
COM1
8-pin
P W 2
ATX PWR
JPF
Force
PW-On
Mic
J 2 6
Audio
Enable
SI/O
PCI-E (x16)
PCI-X (66 MHz)
PCI-X (66 MHz)
Battery
W O R
JPS1
F
AN1
LAN1
Aux in
CDin
PCI (33MHz)
J 1 3 J 1 5
JPL1
Floppy
PW LED/KL
SA
TA
2
Chassis
Intrusion
Hance
Rapids
USB2/3
JF1
JBT1
J W D
J 6
Dn:Line_In
Up:Line_Out
J 4 1
J35
JSLED
SA
TA
LED
SA
TA
I
2
C
(*X
6D
A
L-X
TG
)
Watch
D o g
LAN1 Enable
Fan5
Fan6
JWOL
J F 2 Spkr
CL CMOS
Fan4
FP Ctlr
Fan3
Fan2
CPU2
CPU1
SMB data toPCIEn.
SMBCLKtoPCI En.
CN1
AlMRset
J 2 7
J 7
P W
Fault
SMB PW
J 2
J 4
J 5
PCI (33MHz)
J 3
P W 1
PW3
J 4 3
LAN
CTRL
BIOS
Printer
Spkr
SA
TA
0
SA
TA
3
SA
TA
1
JL1
SATA
CTRL
Marvell SATA
Enable
H-SA
T
A
0
H-SA
T
A
1
JS0
JS1
DS1
DS3
DS6
DS2
DS5
DS7
DS8
DS9
IDE
Содержание X6DAL-XTG
Страница 1: ...X6DAL XTG USER S MANUAL Revision 1 0 SUPER...
Страница 9: ...Chapter 1 Introduction 1 3 Introduction Figure 1 1 SUPER X6DAL XTG Image...
Страница 84: ...B 8 X6DAL XTG User s Manual Notes...
Страница 106: ...C 22 X6DAL XTG User s Manual Notes...
Страница 126: ...D 20 X6DAL XTG User s Manual Notes...