Supero Supero X7SB4, Руководство пользователя

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Chapter 1: Introduction
1-9
1-2 Chipset Overview
The Intel 3210 Chipset, designed for use with the Xeon 3000 Series Processor,
is comprised of two primary components: the Memory Controller Hub (MCH)
and the I/O Controller Hub (ICH9R). In addition, Intel's PCI-X (PXH) is used for
added functionality. The X7SB4/X7SBE provides the performance and feature-set
required for the cutting-edge, cost-effective server market.
Memory Controller Hub (MCH)
The function of the MCH is to manage the data fl ow between four interfaces: the
CPU interface, the DDR2 System Memory Interface, the PCI Express Interface,
and the Direct Media Interface (DMI). The MCH is optimized for the Xeon Core™2
processor in the 45nm/65nm process in the LGA775 Land Grid Array Package.
It supports one or two channels of DDR2 SDRAM.
The I/O Controller (ICH9R) provides the data buffering and interface arbitration re-
quired for the system to operate effi ciently. It also provides the bandwidth needed
for the system to maintain its peak performance. The Direct Media Interface (DMI)
provides the connection between the MCH and the ICH9R. The ICH9R supports
two PCI-Express devices, six Serial ATA ports, and up to seven USB 2.0 ports/
headers. In addition, the ICH9R offers the Intel Matrix Storage Technology which
provides various RAID options for data protection and rapid data access. It also
supports the next generation of client management through the use of PROActive
technology in conjunction with Intel's next generation Gigabit Ethernet controller.
Intel ICH9R System Features
The I/O Controller Hub provides the I/O subsystem with access to the rest of the
system. Functions and capabilities include:
*Advanced Confi guration and Power Interface, Version 2.0 (ACPI)
*Intel I/O External Design Specifi cation (EDS)
*3210 Memory Controller Hub (MCH) External Design Specifi cation (EDS)
*Intel I/O Controller Hub 9 (ICH9R ) Thermal Design Guideline
*Intel 82573 V/L Platform LAN Connect (PLC) PCI Design