Supero Supero X7QC3, Руководство пользователя

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X7QC3/X7QCE User’s Manual
Branch 0 Rank Sparing/Branch 1 Rank Sparing
Select Enabled to enable the sparing feature for Branch 0 or Branch 1 of the
memory bus. The options are Enabled and Disabled .
Branch 0 Rank Interleaving/Branch 1 Rank Interleaving
Select Enable to enable the functions of Memory Interleaving for Branch 0 Rank
or Branch 1 Rank. The options for Memory Interleaving are 1:1, 2:1 and 4:1 .
FBD Throttling
Select Enabled to use the feature of closed-loop thermal throttling on a fully
buffered (FBD) memory module. If Enabled, thermal throttling will be activated
when the temperature of an FBD module reaches a predefi ned threshold. The
default setting is Enabled .
Spread Spectrum Mode
If Enabled, the BIOS will monitor the level of Electromagnetic Interference
caused by the components and will attempt to decrease the interference
whenever needed. The options are Enabled and Disabled .
Non-Compliance Mode
Select the Compliance Mode to enable the PCI-Express Compliance Mode.
The options are Non-Compliance and Compliance.
South Bridge Confi guration
This feature allows the user to confi gure the Intel ICH South Bridge settings.
SMBus Controller
Select Enabled to activate the onboard SMBus (System Management Bus)
controller. The options are Enabled and Disabled.
USB Functions
This feature allows the user to decide the number of onboard USB ports to be
enabled. The Options are: Disabled, 2 USB ports, 4 USB ports, and 6 USB
ports .
USB2.0 Controller
Select Enabled to activate the onboard USB2.0 controller. The options are
Enabled and Disabled.
SLP_S4# Minimum Assertion Width
This setting allows the user to select a desired length of time to be used as
the SLP_S4# Min. Assertion Width. The options are 4-5 Sec., 3-4 Sec., 2-3
Sec., and 1-2 Sec.