Supero SUPER P6DGE, Руководство пользователя и BIOS

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BIOS User's Manual
5-8
tions:
- In an ECC configuration, the GX asserts SERR#, for single bit (correctable) ECC errors or multiple bit
(non-correctable) ECC errors if SERR# signaling is enabled via the ERRCMD control register. Any ECC
errors received during initialization should be ignored.
- The GX asserts SERR# for one clock when it detects a target abort during GX initiated PCI cycle
- The GX can also assert SERR# when a PCI parity error occurs during the address or data phase
- The GX can assert SERR# when it detects a PCI address or data parity error on AGP
- The GX can assert SERR# upon detection of access to an invalid entry in the Graphics Aperature
Translation Table
- The GX can assert SERR# upon detecting an invalid AGP master access outside of AGP aperture and
outside of main DRAM range (i.e. in the 640k - 1M range or above TOM)
- The GX can assert SERR# upon detecting an invalid AGP master access outside of AGP aperture.
- The GX asserts SERR# for one clock when it detects a target abort during GX initiated AGP cycle
PERR#
The settings for this option are Enabled or Disabled. Set to Enabled to
enable the PERR# signal on the bus.
WSC# Handshake (Write Snoop Complete)
This signal is asserted active to indicate that all the snoop activity on the
CPU bus on the behalf of the last PCI-DRAM write transaction is complete
and that it is safe to send the APIC interrupt message. The settings for
this option are Enabled or Disabled. Set to Enabled to enable hand-
shaking for the WSC# signal.
USWC Write Post
The settings for this option are Enabled or Disabled. This option sets
the status of USWC (Uncacheable, Speculatable, Write-Combined) posted
writes. Set to Enabled to enable USWC posted writes to I/O. Set to
Disabled to disable USWC posted writes to I/O.
Bus Master Latency Timer (CLKs)
This option specifies the master latency timings (in PCI clocks) for
devices in the computer. The settings are Disabled, 32, 64, 96, 128,
160, 192 or 224.
Multi-Trans Timer (Clks)
This option specifies the multi-trans latency timings (in PCI clocks) for
devices in the computer. The settings are Disabled, 32, 64, 96, 128,
160, 192 or 224.