41
Chapter 2: Installation
Symmetric Population
1-1-1
(For Channel Con
fi
guration: 1-1-1)
Modes
CPU1
P1-DIMMF1
P1-DIMMF2
P1-DIMME1
P1-DIMME2
P1-DIMMD1
P1-DIMMD2
P1-DIMMA2
P1-DIMMA1
P1-DIMMB2
P1-DIMMB1
P1-DIMMC2
P1-DIMMC1
AD
DCPMM
-
DRAM1
-
DRAM1
-
-
DRAM1
-
DRAM1
-
DCPMM
MM
DCPMM
-
DRAM1
-
DRAM1
-
-
DRAM1
-
DRAM1
-
DCPMM
AD + MM
DCPMM
-
DRAM3
-
DRAM3
-
-
DRAM3
-
DRAM3
-
DCPMM
CPU2
P2-DIMMF1
P2-DIMMF2
P2-DIMME1
P2-DIMME2
P2-DIMMD1
P2-DIMMD2
P2-DIMMA2
P2-DIMMA1
P2-DIMMB2
P2-DIMMB1
P2-DIMMC2
P2-DIMMC1
AD
DCPMM
-
DRAM1
-
DRAM1
-
-
DRAM1
-
DRAM1
-
DCPMM
MM
DCPMM
-
DRAM1
-
DRAM1
-
-
DRAM1
-
DRAM1
-
DCPMM
AD + MM
DCPMM
-
DRAM3
-
DRAM3
-
-
DRAM3
-
DRAM3
-
DCPMM
CPU3
P3-DIMMF1
P3-DIMMF2
P3-DIMME1
P3-DIMME2
P3-DIMMD1
P3-DIMMD2
P3-DIMMA2
P3-DIMMA1
P3-DIMMB2
P3-DIMMB1
P3-DIMMC2
P3-DIMMC1
AD
DCPMM
-
DRAM1
-
DRAM1
-
-
DRAM1
-
DRAM1
-
DCPMM
MM
DCPMM
-
DRAM1
-
DRAM1
-
-
DRAM1
-
DRAM1
-
DCPMM
AD + MM
DCPMM
-
DRAM3
-
DRAM3
-
-
DRAM3
-
DRAM3
-
DCPMM
CPU4
P4-DIMMF1
P4-DIMMF2
P4-DIMME1
P4-DIMME2
P4-DIMMD1
P4-DIMMD2
P4-DIMMA2
P4-DIMMA1
P4-DIMMB2
P4-DIMMB1
P4-DIMMC2
P4-DIMMC1
AD
DCPMM
-
DRAM1
-
DRAM1
-
-
DRAM1
-
DRAM1
-
DCPMM
MM
DCPMM
-
DRAM1
-
DRAM1
-
-
DRAM1
-
DRAM1
-
DCPMM
AD + MM
DCPMM
-
DRAM3
-
DRAM3
-
-
DRAM3
-
DRAM3
-
DCPMM
Asymmetric Population
2/1-
1-1
(For Channel Con
fi
guration: 2/1-1-1)
Modes
CPU1
P1-DIMMF1 P1-DIMMF2 P1-DIMME1 P1-DIMME2 P1-DIMMD1
P1-DIMMD2
P1-DIMMA2
P1-DIMMA1
P1-DIMMB2
P1-DIMMB1
P1-DIMMC2
P1-DIMMC1
AD
DRAM1
-
DRAM1
-
DRAM1
-
DCPMM
DRAM1
-
DRAM1
-
DRAM1
CPU2
P2-DIMMF1 P2-DIMMF2 P2-DIMME1 P2-DIMME2 P2-DIMMD1
P2-DIMMD2
P2-DIMMA2
P2-DIMMA1
P2-DIMMB2
P2-DIMMB1
P2-DIMMC2
P2-DIMMC1
AD
DRAM1
-
DRAM1
-
DRAM1
-
DCPMM
DRAM1
-
DRAM1
-
DRAM1
CPU3
P3-DIMMF1 P3-DIMMF2 P3-DIMME1 P3-DIMME2 P3-DIMMD1
P3-DIMMD2
P3-DIMMA2
P3-DIMMA1
P3-DIMMB2
P3-DIMMB1
P3-DIMMC2
P3-DIMMC1
AD
DRAM1
-
DRAM1
-
DRAM1
-
DCPMM
DRAM1
-
DRAM1
-
DRAM1
CPU4
P4-DIMMF1 P4-DIMMF2 P4-DIMME1 P4-DIMME2 P4-DIMMD1
P4-DIMMD2
P4-DIMMA2
P4-DIMMA1
P4-DIMMB2
P4-DIMMB1
P4-DIMMC2
P4-DIMMC1
AD
DRAM1
-
DRAM1
-
DRAM1
-
DCPMM
DRAM1
-
DRAM1
-
DRAM1
Legend (for the
fi
ve tables above)
DDR4 Type
Capacity
DRAM1
RDIMM
3DS RDIMM
LRDIMM
3DS LRDIMM
Refer to Validation Matrix
(DDR4 DIMMs validated with
DCPMM) on the next page.
DRAM2
RDIMM
-
-
DRAM3
RDIMM
3DS RDIMM
LRDIMM
-
Note
: DDR4 single rank x8 is not available for DCPMM Memory Mode or App-Direct Mode.
Legend (for the
fi
rst
fi
ve tables above)
Capacity
DCPMM
Any Capacity (Uniformly for all channels for a given con
fi
guration)
•
For MM, general NM/FM ratio is between 1:4 and 1:16. Excessive capacity for FM can be used for AD. (NM = Near
Memory; FM = Far Memory)
•
For each individual population, rearrangements between channels are allowed as long as the resulting population is
compliant with the PDG rules for the 2nd Gen Intel Xeon Scalable-SP (82xx/62xx/52xx/42xx series) processors.
•
For each individual population, please use the same DDR4 DIMM in all slots.
•
For each individual population, sockets are normally symmetric with exceptions for 1 DCPMM per socket and 1 DCPMM
per node case.
•
No mixing of DCPMM and NVMDIMMs within the same platform is allowed.
•
This DCPMM population guide targets a balanced DCPMM-to-DRAM-cache ratio in MM and MM + AD modes.
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