17
Chapter 1: Introduction
Figure 1-7. Motherboard Layout
1.4 Motherboard Layout
Below is a layout of the X12SPI-TF motherboard with jumper, connector and LED locations
shown. See the table on the following page for descriptions. For detailed descriptions, pinout
information and jumper settings, refer to
or the
BIOS LICENSE
BAR CODE
MAC CODE
SAN MAC
DESIGNED IN USA
X12SPi-TF
REV: 2.00
IPMI CODE
PCH
621A
BMC
AST2600
X550
S-SGPIO1
JBT1
JPWR2
JSD2
JSD1
S-SA
TA1
S-SA
TA0
JSTBY1
JRK1
JPWR3
JPWR1
JNCSI
JF1
JVRM2
JVRM1
JPFR3
JPFR2
JPFR1
JL1
JPRG1
JPCK1
JPME1
JP4
FAN4 FAN3
FANB FANA
FAN5
FAN2
FAN1
NVME0/1
MH16
MH15
UID_SW
JPI2C1
JI2C_EXP1
JNVI2C
JIPMB1
MH4
MH6
MH1
MH9
MH8
MH7
MH5
MH3
MH2
VGA
JMP1 JMP2
BT1
LEDPWR
I-SA
TA4~7
M.2-H
COM1
DIMMG1 DIMMH1 DIMME1 DIMMF1
DIMMA1
DIMMB1
DIMMD1 DIMMC1
CPU
USB8(3.2 Gen 1)
USB6/7(3.2 Gen 1)
USB2/3
IPMI_LAN
LAN2
LAN1
I-SA
TA0~3
TPM/POR
T80
UID
-LED
CPU SLOT7 PCI-E 4.0 X8
CPU SLOT6 PCI-E 4.0 X16
CPU SLOT4 PCI-E 4.0 X16
CPU SLOT2 PCI-E 4.0 X8(IN X16)
CPU SLOT1 PCI-E 4.0 X8
USB4/5 (3.0)
LE4
USB 0/1
LEDBMC
JI2C_FP1
COM1
JIPMB1
JPME1
JI2C_FP1
USB2/3
USB6/7
(3.2 Gen 1)
DIMMG1
DIMMH1
DIMME1
DIMMF1
DIMMB1
DIMMA1
DIMMD1
DIMMC1
FAN5
JPWR1
JPWR2
JSD1
S-SATA1
I-SATA0~3
I-SATA4~7
S-SATA0
TPM/PORT80
JBT1
BT1
JL1 S-SGPIO1
FANB
FANA
SLOT1
SLOT2
SLOT4
SLOT6
SLOT7
JPRG1
JNCSI
UID-LED
UID_SW
VGA
LAN2
LAN1
USB4/5 (3.2 Gen 1)
BMC_LAN
NVME0/1
M.2-H
JRK1
USB8 (3.2 Gen 1)
JP4
LED_PWR
JF1
FAN4
FAN3
JVRM1
JVRM2
JSTBY1
JNVI2C
JI2C_EXP1
JPWR3
JPI
2
C1
FAN2
FAN1
CPU
USB0/1
JSD2
LE4
LEDBMC