Supermicro PDSBA, Руководство пользователя

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Chapter 4: BIOS
4-13
Select Write Protect to prevent data from being written into the base memory area
of Block 512K-640K. Select Write Back to allow the CPU to write data back directly
from the buffer without writing data to the System Memory for fast CPU data pro-
cessing and operation. The options are Uncached, Write Through, Write Protect,
and Write Back .
Cache Extended Memory
If enabled, this feature will allow the data stored in the extended memory area to
be cached (written) into a buffer, a storage area in the Static DROM (SDROM) or
written into L1, L2 or L3 cache inside the CPU to speed up CPU operations. Select
Uncached to disable this function. Select Write Through to allow data to be cached
into the buffer and written into the system memory at the same time. Select Write
Protect to prevent data from being written into the extended memory area above 1
MB. Select Write Back to allow the CPU to write data back directly from the buffer
without writing data to the System Memory for fast CPU data processing and opera-
tion. The options are Uncached, Write Through, Write Protect, and Write Back .
Discrete MTRR Allocation
If enabled, MTRRs (-Memory Type Range Registers) are confi gured as distinct,
separate units and cannot be overlapped. If enabled, the user can achieve better
graphic effects when using a Linux graphic driver that requires the write-combining
confi guration with 4GB or more memory. The options are Enabled and Disabled .
PCI Confi guration
Access the submenu to make changes to the following settings for PCI devices.
PCI 33 MHz Slot#1- PCI 33 MHz Slot#4
Access the submenu for each of the settings above to make changes to the
following:
Option ROM Scan
When enabled, this setting will initialize the device expansion ROM. The options
are Enabled and Disabled.
Enable Master
This setting allows you to enable the selected device as the PCI bus master.
The options are Enabled and Disabled.
Latency Timer
This setting allows you to set the clock rate for the Bus Master. A high-priority,
high-throughout device may benefi t from a greater clock rate. The options are