SIS Documentation
SIS3820
VME Scaler
Page 69 of 79
15.9 CBLT readout (3820 01 03 and higher design)
CBLT is a method to speed up the readout of small amounts of data from a larger number of
slaves in conjunction with long setup time masters. As header and trailer words are added in
CBLT, this readout approach is less efficient than low setup overhead list sequencer readout
of masters like the SIS3100 VME sequencer.
Modules which are supposed to participate in a CBLT have to get the same CBLT address, in
the case of the SIS3820 the CBLT address is defined by the upper 8 bits of the CBLT setup
register . The module closest to the CPU has to be defined as “First” CBLT module, the
module at the end of the chain is defined as “Last” CBLT module. All modules have to have
their CBLT enable bit set, the modules must occupy a contiguous set of VME slots as shown
in the sketch below. The token is passed from the previous module to the next module via the
IRQ daisy chain lines as soon as all data have been read. The last module in the chain
terminates the transfer with a VME bus error (BERR). .
VME Crate
CPU
First
Last
Middle
Middle
Schematic CBLT setup
The SIS3820 supports the CBLT readout mode only in the MCS (Multiscaler) mode in FIFO
mode !
