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SIS Documentation 

SIS3820 

VME Scaler 

 

 

Page 4 of 79 

7.18.9

 

Clearing/non clearing .................................................................................................................... 39

 

7.19

 

Copy disable register (0x104) ............................................................................................................... 40

 

7.20

 

LNE channel select register (0x108) ..................................................................................................... 41

 

7.21

 

PRESET channel select register (0x10C).............................................................................................. 42

 

7.21.1

 

Preset scheme ................................................................................................................................ 42

 

7.22

 

MUX OUT channel select register (0x110) .......................................................................................... 43

 

7.23

 

Inhibit/count disable register (0x200) ................................................................................................... 44

 

7.24

 

Counter clear register (0x204)............................................................................................................... 44

 

7.25

 

Counter Overflow register (0x208) ....................................................................................................... 44

 

7.26

 

Channel 1/17 Bits 33-48 register (0x210) ............................................................................................. 45

 

7.27

 

Veto external count inhibit register (0x214) ......................................................................................... 45

 

7.28

 

Test pulse mask  register (0x218) ......................................................................................................... 46

 

7.29

 

SDRAM SPD register (0x300).............................................................................................................. 46

 

7.30

 

JTAG_TEST register ............................................................................................................................ 47

 

7.31

 

JTAG_DATA_IN register..................................................................................................................... 47

 

7.32

 

JTAG_CONTROL register ................................................................................................................... 47

 

7.33

 

One wire Id. register (tbd)..................................................................................................................... 48

 

7.34

 

FIFO address space (0x800000-0xFFFFFC)......................................................................................... 49

 

7.34.1

 

non incrementing VME master ..................................................................................................... 49

 

7.34.2

 

incrementing VME master ............................................................................................................ 49

 

7.35

 

SDRAM address space (0x800000-0xFFFFFC) ................................................................................... 49

 

8 Data 

Format ....................................................................................................................... 50 

8.1

 

32-bit Mode........................................................................................................................................... 50

 

8.2

 

24-bit Mode........................................................................................................................................... 50

 

8.3

 

16-bit Mode........................................................................................................................................... 51

 

8.4

 

8-bit Mode............................................................................................................................................. 51

 

9 Front 

panel 

elements.......................................................................................................... 52 

9.1

 

Front Panel Layout................................................................................................................................ 52

 

9.2

 

Front Panel LEDs.................................................................................................................................. 53

 

9.3

 

Flat cable Input/Output Pin Assignments.............................................................................................. 54

 

9.3.1

 

ECL ............................................................................................................................................... 54

 

9.3.2

 

TTL ............................................................................................................................................... 55

 

10 Board 

Layout.................................................................................................................. 56 

11 Jumper 

settings/pinouts .................................................................................................. 57 

11.1

 

J1 ........................................................................................................................................................... 57

 

11.2

 

J90 ......................................................................................................................................................... 57

 

11.3

 

JP570 JTAG source............................................................................................................................... 58

 

11.4

 

CON500 JTAG ..................................................................................................................................... 58

 

12 Input 

Configuration ........................................................................................................ 59 

12.1

 

ECL ....................................................................................................................................................... 59

 

12.2

 

LVDS .................................................................................................................................................... 60

 

12.3

 

NIM....................................................................................................................................................... 61

 

12.4

 

TTL ....................................................................................................................................................... 62

 

12.4.1

 

High impedance TTL/LEMO........................................................................................................ 62

 

12.4.2

 

50

Ω

 TTL/LEMO........................................................................................................................... 62

 

12.4.3

 

TTL/Flat Cable.............................................................................................................................. 62

 

13 

TTL output configuration............................................................................................... 63 

14 Signal 

Specification........................................................................................................ 63 

14.1

 

Control Signals...................................................................................................................................... 63

 

14.2

 

Inputs..................................................................................................................................................... 63

 

14.3

 

User Bits................................................................................................................................................ 63

 

15 

Theory of operation........................................................................................................ 64 

15.1

 

Enable Logic ......................................................................................................................................... 64

 

15.2

 

Read on the fly ...................................................................................................................................... 65

 

15.3

 

Latching scaler ...................................................................................................................................... 65

 

15.4

 

Preset Scaling........................................................................................................................................ 65

 

15.5

 

Multiscaling (MCS) .............................................................................................................................. 66

 

15.5.1

 

Minimum dwell time..................................................................................................................... 66

 

Содержание SIS3820

Страница 1: ...ge 1 of 79 SIS3820 VME Scaler User Manual SIS GmbH Harksheider Str 102A 22399 Hamburg Germany Phone 49 0 40 60 87 305 0 Fax 49 0 40 60 87 305 20 email info struck de http www struck de Version sis3820...

Страница 2: ...0 1 31 09 11 04 Bug fix in address map change FIFO threshold register explanation 1 32 13 01 05 Couple of index entries added typo fix 1 40 20 05 05 Firmware Version 01 05 New Control Output mode 2 10...

Страница 3: ...Register 0x4 read 21 7 2 1 Major revision numbers 21 7 3 Interrupt configuration register 0x8 22 7 3 1 IRQ mode 22 7 4 Interrupt Control Status register 0xC 23 7 4 1 Interrupt sources 24 7 5 0x10 Acqu...

Страница 4: ...FC 49 7 34 1 non incrementing VME master 49 7 34 2 incrementing VME master 49 7 35 SDRAM address space 0x800000 0xFFFFFC 49 8 Data Format 50 8 1 32 bit Mode 50 8 2 24 bit Mode 50 8 3 16 bit Mode 51 8...

Страница 5: ...BLT readout 3820 01 03 and higher design 69 15 9 1 CBLT Setup example 70 15 9 2 CBLT hints 71 15 10 Broadcast 71 16 Appendix 72 16 1 P2 row A C pin assignments 72 16 2 Row d and z Pin Assignments 73 1...

Страница 6: ...SIS Documentation SIS3820 VME Scaler Page 6 of 79...

Страница 7: ...concept of flexible leaded component based frontend circuitry in conjunction with more recent FPGA field programmable gate array technology results in unprecedented flexibility to implement the given...

Страница 8: ...ate ECL and NIM 100 MHz for TTL 50 MHz for P2 fed channels 32 bit counter depth channel 1 and 17 48 bit deep with firmware 01 04 in scaler mode NIM TTL ECL LVDS versions flat cable ECL TTL and LVDS an...

Страница 9: ...tworks The firmware is loaded from a serial PROM at power up Both JTAG and VME can be used for in field firmware upgrades changes 4 1 Block Diagram SDRAM 4 x Level Adaptation Driver Receiver 4 x Level...

Страница 10: ...escale factor stored into the channel 1 preset value register The terminating channel can be identified by the actual scaler data or the preset hit mask register if more than one preset channel is ena...

Страница 11: ...our SIS3820 board in the VME crate connect inputs turn VME crate power back on verify that the P power and R ready LEDs are on and all other LEDs are off after the approximately 2s long power up self...

Страница 12: ...0000000 ch14 00000000 ch15 00000000 ch16 00000000 ch17 03477ce7 ch18 00000000 ch19 00000000 ch20 00000000 ch21 00000000 ch22 00000000 ch23 00000000 ch24 00000000 ch25 00000000 ch26 00000000 ch27 00000...

Страница 13: ...LED is on from the enable command until the acquisition preset has been reached mki mki sis1100 sis3820 sis3820_mcs MCS mode scan 1 completed MCS mode scan 2 completed MCS mode scan 3 completed MCS mo...

Страница 14: ...000000 ch07 00000000 ch08 00000000 ch09 00000000 ch10 00000000 ch11 00000000 ch12 00000000 ch13 00000000 ch14 00000000 ch15 00000000 ch16 00000000 ch17 00000000 ch18 00000000 ch19 00000000 ch20 000000...

Страница 15: ...3820 VME Scaler Page 15 of 79 5 3 Win2K XP Visual C example test code Find below a screen shot of the Visual C directory of the SIS36 38xx CDROM A short description is given in the header section of t...

Страница 16: ...J1 SDRAM_SIZE closed 512 MBytes EN_A32 EN_GEO Description 0 0 non A32 addressing reserved for future use 0 1 non A32 addressing reserved for future use 1 0 A32 addressing address compared with SW3 SW...

Страница 17: ...n mode register 0x104 R W D32 Copy disable register 0x108 R W D32 LNE channel select register 1 of 32 0x10C R W D32 PRESET channel select register 2 times 1 out of 16 0x110 R W D32 MUX_OUT channel sel...

Страница 18: ...t in a VME bus error In MCS mode the memory is reserved for storage of the counter values 2 firmware 01 0A indicates revision 01 0A and higher unless otherwise The shorthand KA stands for key address...

Страница 19: ...unction 31 Status external LATCH Bit2 depending on Input Mode 30 Status external LATCH Bit1 depending on Input Mode 29 Status external Input Bit2 depending on Input Mode 28 Status external Input Bit1...

Страница 20: ...25 MHz test pulses if this bit and the counter test mode bit is set From firmware 01 0A on you can use the test pulse mask register to exclude selected channels from participating in test pulse count...

Страница 21: ...it 10 25 Module Id Bit 9 24 Module Id Bit 8 8 23 Module Id Bit 7 22 Module Id Bit 6 21 Module Id Bit 5 20 Module Id Bit 4 2 19 Module Id Bit 3 18 Module Id Bit 2 17 Module Id Bit 1 16 Module Id Bit 0...

Страница 22: ...abled as soon as the interrupt is acknowledged by the CPU After the interrupt is serviced the source has to be activated with the enable VME IRQ source bit again ROAK IRQ mode can be used in conjuncti...

Страница 23: ...source 5 0 20 Clear IRQ source 4 Status flag source 4 0 19 Clear IRQ source 3 Status flag source 3 0 18 Clear IRQ source 2 Status flag source 2 0 17 Clear IRQ source 1 Status flag source 1 0 16 Clear...

Страница 24: ...nt signal The interrupt is issued whenever a LNE signal triggers scaler value transfer to memory The interrupt will be induced by the rundown of the preset value if LNE prescaling is active In scaler...

Страница 25: ...hed in preset scaler mode 7 4 1 4 Overflow IRQ source 3 level sensitive The overflow interrupt source is triggered if one or more counters exceed the 32 bit range The overflow registers can be used to...

Страница 26: ...so it is not associated with a direct interrupt Interrupt generation can be accomplished in conjunction with the acquisition completed IRQ source 2 edge sensitive The status flag of the active mode sc...

Страница 27: ...cale factor bit 0 If the new prescale factor is supposed to have an immediate effect i e if the new prescale factor and the input rate are smaller than the previous setting following sequence has to b...

Страница 28: ...e and Hit register 0x28 define SIS3820_PRESET_ENABLE_HIT 0x28 read write D32 This register is used to enable one or both counter groups for preset operation and provides the information which group ha...

Страница 29: ...dcast address bit 25 24 CBLT Broadcast address bit 24 23 CBLT MAX Readout Length Bit 7 22 CBLT MAX Readout Length Bit 6 21 CBLT MAX Readout Length Bit 5 20 CBLT MAX Readout Length Bit 4 19 CBLT MAX Re...

Страница 30: ...be incremented automatically during a block transfer BLT32 MBLT64 2eVME beyond a page boundary This will allow you to read large chunks of memory with the SIS3100 VME sequencer and similar hardware in...

Страница 31: ...rd counter application SDRAM Address pointers non VME accessible In FIFO Mode the write pointer is reset upon SIS3820_KEY_RESET and SIS3820_KEY_SDRAM_FIFO_RESET the write pointer is incremented upon S...

Страница 32: ...n as the number of data words in the SDRAM exceeds the threshold Bit Function 31 none read as 0 28 none read as 0 27 none read as 0 26 FIFO word counter threshold bit 26 1 FIFO word counter threshold...

Страница 33: ...DISABLE command is issued 7 16 HISCAL_START_COUNTER register 0x44 define SIS3820_HISCAL_START_COUNTER 0x44 read only D32 This 32 bit deep register holds the number of scans starts in HISCAL operation...

Страница 34: ...1 0 16 Control input mode bit 0 0 15 reserved 0 14 HISCAL_START_SOURCE_BIT 0 13 select SDRAM add mode 0 12 select SDRAM mode 0 11 Reserved 0 10 Reserved 0 9 Arm Enable source bit 1 0 8 Arm Enable sour...

Страница 35: ...ernal user bit 1 input 3 inhibit counting input 4 inhibit LNE Mode 3 input 1 external next pulse LNE clock shadow bit2 0 bit1 1 bit0 1 input 2 external user bit 1 input 3 external user bit 2 input 4 i...

Страница 36: ...de CIP bit1 0 bit0 1 output 6 Enabled output 7 50 MHz output 8 User output User LED Mode 2 output 5 Scaler mode LNE pulse MCS Mode CIP bit1 1 bit0 0 output 6 10 MHz 20ns pulse output 7 10 MHz 20ns pul...

Страница 37: ...amming scaler operation SDRAM add mode bit SDRAM mode bit Mode 0 0 FIFO emulation 0 1 SDRAM 1 0 SDRAM 1 1 SDRAM 7 18 6 Arm enable source The two arm enable source bits define what signal the enable is...

Страница 38: ...signal 0 1 0 10 MHz internal pulser 0 1 1 Channel N ChN 1 0 0 Preset Scaler N MCS only LNE sources can be prescaled with the LNE prescaler where needed The LNE prescaler is active if the prescale fact...

Страница 39: ...t 0 1 24 bit with user bit and channel information 1 0 16 bit MCS only 1 1 8 bit MCS only A more detailed description of the data formats is given in section 8 7 18 9 Clearing non clearing This bit de...

Страница 40: ...bit channel 32 0 copy disable bit channel 1 Examples If 0xFFFF is written to the copy disable register channels 17 through 32 data will be copied to memory if 0xFFFF0000 is set channels 1 through 16...

Страница 41: ...channel has to be selected before the counting process is started and can not be changed during acquisition Bit Function 31 no function read as 0 5 no function read as 0 4 bit 4 of LNE channel 3 2 1...

Страница 42: ...ad as 0 19 bit 3 of PRESET channel select group2 18 17 16 bit 0 of PRESET channel select group2 15 no function read as 0 4 no function read as 0 3 bit 3 of PRESET channel select group1 2 1 0 bit 0 of...

Страница 43: ...e a visual rate meter e g Register Bit assignments Bit Function 31 no function read as 0 5 no function read as 0 4 bit 4 of OUT_MUX channel 3 2 1 0 bit 0 of OUT_MUX channel Notes 1 The power up defaul...

Страница 44: ...Counter clear register 0x204 define SIS3820_COUNTER_CLEAR 0x204 write only D32 On write access to this register each channel can be cleared individually by the setting of the corresponding bit Bit wr...

Страница 45: ...can be used to veto the external inhibit input modes 1 2 3 4 and 6 for individual scaler channels By default the veto function is switched off for all channels Bit Function 31 Veto external count inhi...

Страница 46: ...ups You can use the 25 MHz test pulser on channels 9 17 and 25 and the 50 MHz reference pulser on channel 1 e g in combination with the proper veto external count inhibit pattern set to measure the in...

Страница 47: ...n the firmware upgrade process over VME only It is at the same address as the JTAG_TEST register and is used in read access It operates as a shift register for TDO The contents of the register is shif...

Страница 48: ...x00 7 Serial Number 0x0A Note Module Id and SDRAM size are stored in hexadecimal form for better readability the serial number is stored as straight 32 bit decimal value Refer to the PDF data sheet of...

Страница 49: ...FO mode e g you can read an arbitrary amount of data typically defined by the current value of the FIFO word counter register in one block transfer from the first address of the FIFO address space Blo...

Страница 50: ...he data word contains the straight scaler contents in this mode Bits 31 24 Bits 23 16 Bits 15 8 Bits 7 0 Data Bits 31 24 Data Bits 23 16 Data Bits 15 8 Data Bits 7 0 8 2 24 bit Mode The lower 24 bits...

Страница 51: ...e Bits 31 24 Bits 23 16 Bits 15 8 Bits 7 0 Scaler channel N 1 bits 15 0 Scaler channel N bits 15 0 8 4 8 bit Mode The data word contains the straight scaler contents in this mode Bits 31 24 Bits 23 16...

Страница 52: ...rouped to one 8 channel block and the counter inputs are grouped into 2 blocks of 16 channels A mixed LEMO control flat cable counter input version is available also The units are 4 TE one VME slot wi...

Страница 53: ...figured logic U VME user LED green To be switched on off under user program control CLR Clear yellow MCS mode signals LNE Latching scaler signals soft or hardware clear OVL Overflow red Signals Overlo...

Страница 54: ...IN9 17 18 IN25 IN25 17 16 IN8 IN8 15 16 IN24 IN24 15 14 IN7 IN7 13 14 IN23 IN23 13 12 IN6 IN6 11 12 IN22 IN22 11 10 IN5 IN5 9 10 IN21 IN21 9 8 IN4 IN4 7 8 IN20 IN20 7 6 IN3 IN3 5 6 IN19 IN19 5 4 IN2...

Страница 55: ...IN9 GND 17 18 IN25 GND 17 16 IN8 GND 15 16 IN24 GND 15 14 IN7 GND 13 14 IN23 GND 13 12 IN6 GND 11 12 IN22 GND 11 10 IN5 GND 9 10 IN21 GND 9 8 IN4 GND 7 8 IN20 GND 7 6 IN3 GND 5 6 IN19 GND 5 4 IN2 GND...

Страница 56: ...SIS Documentation SIS3820 VME Scaler Page 56 of 79 10 Board Layout Find below a printout of the top assembly drawing...

Страница 57: ...addressing and geographical A32 addressing A closed position selects the corresponding function Function EN_A32 reserved EN_GEO J1 SDRAM The default setting for a 64 MB unit is EN_A32 closed and all...

Страница 58: ...om a serial PROMs The firmware can be upgraded through VME future option or the JTAG connector A list of firmware designs can be found under http www struck de sis3820firm htm Hardware like the XILINX...

Страница 59: ...hannels by removing the corresponding resistor networks The termination of single control inputs can be disabled with jumpers J101 through J108 an open jumper disables the termination of the correspon...

Страница 60: ...orks The termination of single control inputs can be disabled with jumpers J101 through J108 an open jumper disables the termination of the corresponding channel Network Channels RN10 1 4 RN20 5 8 RN3...

Страница 61: ...ed with jumpers J101 through J108 an open jumper disables the termination of the corresponding channel Network Channels U15 Pins 10 to 6 1 4 U15 Pins 1 to 5 5 8 U35 Pins 10 to 6 9 12 U35 Pins 1 to 5 1...

Страница 62: ...e TTL LEMO input circuitry is sketched below 1 K and 4 7 K termination are available as options A high active version can be implemented by replacing the 74F245 with a 74F640 12 4 2 50 TTL LEMO The hi...

Страница 63: ...n into account for all external signals 14 2 Inputs The SIS3820 is specified for counting rates of 250 MHz for ECL and NIM signals and 100 MHz for the TTL case Thus the minimum high and low level dura...

Страница 64: ...application a key enable command is all that is required to enable the logic in MCS or preset mode other signals like arm and LNE are contributing as shown in the enable logic schematic below The enab...

Страница 65: ...isters in three ways Key VME LNE clock shadow external next pulse LNE clock shadow with input modes 1 2 and 3 read from the counter registers Shadow register data are not altered updated in the normal...

Страница 66: ...trary number of readout cycles under the assumption that the VME master is capable of digesting the generated data rate The time slices or load next event LNE cycles can be defined by following proces...

Страница 67: ...e same lengths angular encoder clock ticks stepper motor ticks as consecutive bins 15 6 Clearing non clearing mode The SIS3820 has two sets of counters The two sets are the actual counters and the old...

Страница 68: ...or 2 configurations in HISCAL mode Number of channels Channel depth bits Dwell time in ns 32 32 4000 4 32 500 Note High word count block transfer access to the SDRAM in parallel to MCS HISCAL acquisit...

Страница 69: ...the SIS3820 the CBLT address is defined by the upper 8 bits of the CBLT setup register The module closest to the CPU has to be defined as First CBLT module the module at the end of the chain is defin...

Страница 70: ...address is 0x45xxxxxx 0x45200805 CBLT Max Readout Length is 32 0x20 D32 words 0x80 bytes 0x45200805 CBLT Geo address is 1 0x45200805 CBLT is enabled and First module in chain A BLT32 read from VME ad...

Страница 71: ...sis module like the VDIS or with an oscilloscope and an extender The requested number of bytes of the CBLT transfer have to be higher than the max number of bytes of the readout data of all participat...

Страница 72: ...P2_CLOCK_H 7 Control 0 P2_CLOCK_L 8 DGND DGND 8 DGND DGND 9 Control 3 P2_START_H 9 Control 2 P2_START_L 10 Control 5 P2_STOP_H 10 Control 4 P2_STOP_L 11 Control 7 P2_TEST_H 11 Control 6 P2_TEST_L 12...

Страница 73: ...onnectors are listed below Position P1 J1 P2 J2 Row z Row d Row z Row d 1 VPC 1 2 GND GND 1 GND 3 4 GND GND 5 6 GND GND 7 8 GND GND 9 GAP 10 GND GA0 GND 11 RESP GA1 12 GND GND 13 GA2 14 GND GND 15 GA3...

Страница 74: ...A SIS3820 CLOCK 32 NIM channels 5 V 3 2 A 16 5 Operating conditions 16 5 1 Cooling Although the SIS3820 is mainly a 2 5 and 3 3 V low power design forced air flow is required for the operation of the...

Страница 75: ...by dividing the number of bytes be the difference of the leading edge of the first DS1 and the trailing edge of the last DS1 Mode Transfer speed BLT32 25 MB s MBLT64 50 MB s 2e VME 88 MB s Note you ha...

Страница 76: ...the frontend FPGA registers to memory registers on the VME FPGA Clock Shadow Initiate copy process of frontend scaler data to register set FPGA Field Programmable Gate Array HISCAL Histogramming Scale...

Страница 77: ...SP 10 dwell time 10 40 ECL 54 59 63 edge sensitive 24 EEPROM 48 EN_A32 16 EN_GEO 16 enable 67 enable logic 64 enable source 37 67 FIFO 67 almost full 31 FIFO address space 49 firmware 58 68 FPGA 74 76...

Страница 78: ...t 63 50 MHz 36 CIP 66 copy in progress 66 enabled 36 SDRAM empty 36 SDRAM threshold 36 user 36 overflow 44 P1 73 P2 73 pin assignments 72 PCB 73 Pin Assignments 54 pin header 74 power consumption 74 p...

Страница 79: ...gnal Specification 63 Control 63 Inputs 63 SIL 9 SIS1100 3100 11 75 SIS3100 30 SIS3100 HISCAL 10 SIS3150 75 sis3820 h 11 75 Software Support 75 SPD 57 SW3 11 16 SW4 11 16 TCK 58 TDC 71 TDI 47 58 TDO 5...

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