SIS Documentation
SIS3820
VME Scaler
Page 30 of 79
7.12 SDRAM page register (0x34)
#define SIS3820_SDRAM_PAGE 0x34 /* read/write; D32 */
This read/write register was implemented to reduce the address space that is occupied by the
SIS3820. The idea is to divide the SDRAM -that can have a size of up to 1024 Mbytes- into 8
MByte pages. The contents of the SDRAM page register defines what 8 MByte page is
addressed. The page will be incremented automatically during a block transfer (BLT32,
MBLT64, 2eVME)beyond a page boundary. This will allow you to read large chunks of
memory with the SIS3100 VME sequencer and similar hardware in one go.
The page number is not modified by the MCS scaler data acquisition process.
Bit Function
31
none, read as 0
... ...
9
none, read as 0
8
memory size bit: 0: 64 MB, 1: 512 MB
7
none, read as 0
6
none, read as 0
5
page number bit 5
4
page number bit 4
3
page number bit 3
used with 512 MByte strip
2
page number bit 2
1
page number bit 1
0
page number bit 0
used with 64 MByte strip
The power up value for the page number is 0.
