SIS Documentation
SIS3820
VME Scaler
Page 49 of 79
7.34 FIFO address space (0x800000-0xFFFFFC)
#define SIS3820_FIFO_BASE 0x800000 /* read only; D32/BLTs */
Scaler data can be read from the FIFO address space in FIFO emulation mode. Both single
cycle (D32) and block transfer modes (BLT32, MBLT64, 2eVME) are supported. The FIFO
address space spans 8 MBytes (or 2 M long words) to allow for block transfer with auto
address incrementing VME masters.
A VME bus error (BERR) is driven actively by the SIS3820 if you attempt to read from an
empty FIFO.
7.34.1 non incrementing VME master
With a non auto incrementing VME master (like the SIS3100 in FIFO mode e.g.) you can
read an arbitrary amount of data (typically defined by the current value of the FIFO word
counter register)in one block transfer from the first address of the FIFO address space.
Blocking into smaller blockletts is handled by the hardware without user intervention. This
results in optimum VME throughput as minimum setup time is involved.
7.34.2 incrementing VME master
Most VME masters use address auto incrementing on block transfers. The FIFO address space
of 8 MBytes is a good compromise for large memories also. The user has to set up several
block transfers to read larger portions of memory.
7.35 SDRAM address space (0x800000-0xFFFFFC)
#define SIS3820_SDRAM_BASE 0x800000 /* read only; D32/BLTs */
For larger memories than 64 MBytes, SDRAM sections (pages) of 64 MBytes are selected
with the SDRAM page register.
