Running the demonstration
UM1011
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Doc ID 18064 Rev 1
Figure 10.
Navigating in the demonstration menus
2.5 Clock
sources
2.5.1 Clock
control
The STM32F100ZET6 internal clocks are derived from the HSE clocked by the external
8 MHz crystal.
In this demonstration application, the various system clocks are configured as follows:
●
The system clock is set to 24 MHz. The PLL is used as the system clock source:
24 MHz.
●
The HCLK frequency is set to 24 MHz.
●
The timer clock (TIMCLK) is set to 24 MHz.
●
PCLK1 is set to 24 MHz.
●
PCLK2 is set to 24 MHz.
Only the RTC is clocked by a 32 kHz external oscillator.
Figure 11
illustrates the clock tree organization for this demonstration.
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