4.15 Inter IC Bus (I
2
C)
1 Intro
2
Electrocardiogram (
Ecg
) Signals
The Electrocardiogram (
Ecg
)
•
Ecg
: electrical manifestation of heart activity recorded
from the body surface
•
monitoring of heart rate
The
Ecg
signal can be recorded fairly easily with surface
electrodes placed on the limbs and/or the chest, see pages
6
–
16
below.
Josef Goette
2
2009
4. The number of data bits between the start and the stop bit is not limited but has to be a full
byte number (8/16 bit).
5. After every data block (8/16 data bit) the receiver pulls the ACK to GND when he has
received the message. The receiver can be the master or the slave (see Figure
6. With the stop bit the transfer is quit. Clock is High, Data changes from Low to High.
M41T81
10/28
Figure 10. Serial Bus Data Transfer Sequence
Figure 11. Acknowledgement Sequence
AI00587
DATA
CLOCK
DATA LINE
STABLE
DATA VALID
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00601
DATA OUTPUT
BY RECEIVER
DATA OUTPUT
BY TRANSMITTER
SCL FROM
MASTER
START
CLOCK PULSE FOR
ACKNOWLEDGEMENT
1
2
8
9
MSB
LSB
Figure 4.19:
I
2
C ACK Sequence
M41T81
10/28
Figure 10. Serial Bus Data Transfer Sequence
Figure 11. Acknowledgement Sequence
AI00587
DATA
CLOCK
DATA LINE
STABLE
DATA VALID
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00601
DATA OUTPUT
BY RECEIVER
DATA OUTPUT
BY TRANSMITTER
SCL FROM
MASTER
START
CLOCK PULSE FOR
ACKNOWLEDGEMENT
1
2
8
9
MSB
LSB
Figure 4.20:
I
2
C data transfer sequence
13/28
M41T81
Figure 15. Alternative READ Mode Sequence
WRITE Mode
In this mode the master transmitter transmits to
the M41T81 slave receiver. Bus protocol is shown
in Figure 16, page 13. Following the START con-
dition and slave address, a logic '0' (R/W=0) is
placed on the bus and indicates to the addressed
device that word address “An” will follow and is to
be written to the on-chip address pointer. The data
word to be written to the memory is strobed in next
and the internal address pointer is incremented to
the next address location on the reception of an
acknowledge clock. The M41T81 slave receiver
will send an acknowledge clock to the master
transmitter after it has received the slave address
see Figure 13, page 12 and again after it has re-
ceived the word address and each data byte.
Figure 16. WRITE Mode Sequence
AI00895
BUS ACTIVITY:
ACK
S
ACK
ACK
ACK
STOP
START
P
SDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n
DATA n+1
DATA n+X
SLAVE
ADDRESS
AI00591
BUS ACTIVITY:
ACK
S
ACK
ACK
ACK
ACK
STOP
START
P
SDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n
DATA n+1
DATA n+X
WORD
ADDRESS (An)
SLAVE
ADDRESS
Figure 4.21:
I
2
C writing data from Master to the Slave.
M41T81
12/28
READ Mode
In this mode the master reads the M41T81 slave
after setting the slave address (see Figure 14,
page 12). Following the WRITE Mode Control Bit
(R/W=0) and the Acknowledge Bit, the word ad-
dress 'An' is written to the on-chip address pointer.
Next the START condition and slave address are
repeated followed by the READ Mode Control Bit
(R/W=1). At this point the master transmitter be-
comes the master receiver. The data byte which
was addressed will be transmitted and the master
receiver will send an Acknowledge Bit to the slave
transmitter. The address pointer is only increment-
ed on reception of an Acknowledge Clock. The
M41T81 slave transmitter will now place the data
byte at address An+1 on the bus, the master re-
ceiver reads and acknowledges the new byte and
the address pointer is incremented to “An+2.”
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume due
to a Stop Condition or when the pointer increments
to any non-clock address (08h-13h).
Note: This is true both in READ Mode and WRITE
Mode.
An alternate READ Mode may also be implement-
ed whereby the master reads the M41T81 slave
without first writing to the (volatile) address point-
er. The first address that is read is the last one
stored in the pointer (see Figure 15, page 13).
Figure 13. Slave Address Location
Figure 14. READ Mode Sequence
AI00602
R/W
SLAVE ADDRESS
START
A
0
1
0
0
0
1
1
MSB
LSB
AI00899
BUS ACTIVITY:
ACK
S
ACK
ACK
ACK
NO ACK
STOP
START
P
SDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n
DATA n+1
DATA n+X
WORD
ADDRESS (An)
SLAVE
ADDRESS
S
START
R/W
SLAVE
ADDRESS
ACK
Figure 4.22:
I
2
C reading data from the Slave
Lukas Kohler
43
