ST STM32F779I-EVAL, Руководство пользователя

Страница: 25 / 80

DocID029088 Rev 3 25/80
UM2036 Hardware layout and configuration
79
1Mx16bit SRAM is connected to the NOR/PSRAM2 bank1 of the FMC interface and both 8-
bit and 16-bit accesses are allowed by BLN0 and BLN1 connected to BLE and BHE of the
SRAM respectively.
The 128-Mbit NOR Flash memory is connected to the NOR/PSRAM1 bank1 of the FMC
interface. The 16-bit operation mode is selected by pull-up resistor connected to BYTE pin
of the NOR Flash memory. The write protection can be enabled or disabled depending on
how the jumper JP16 is set, as shown in
Table 13 :
All signals for memory are also connected on memory connectors CN10 and CN11 for
memory daughterboards.
Some addressing limitations can happen on FMC when using other peripherals.
FMC addresses are limited to:
•
A21 when SAI used
• A20 when camera is used
•
A22 when Ethernet is used
• A20 when RGB LCD is used
•
A18 for 4-bit ETM to A21 for 1-bit ETM when the ETM trace is used
In such cases, memory addresses A19 to A22 not connected to FMC are pulled down, so
that memories can be addressed within a limited address range. If A21 or A22 is required,
the camera board should be removed from the STM32F779I-EVAL board.
6.14 Quad-SPI NOR Flash
The 512-Mbit Quad-SPI NOR Flash is connected to Quad-SPI interface of the
STM32F779NI on the STM32F779I-EVAL evaluation board.
6.15 Analog input
The two-pin header CN3 and 10K ohm potentiometer RV1 is connected to PF10 of the
STM32F779NI as analog input. A low pass filter can be implemented by replacing R29 and
C24 with the right value of the resistor and the capacitor, as requested by end user’s
application.
Table 13. NOR Flash related jumpers
Jumper Description
JP16
Write protection is enabled when JP16 is fitted while write protection is disabled
when JP16 is not fitted.
Default Setting: Not fitted
JP9 PC6 is connected with FMC_NWAIT signal when JP9 is fitted
JP10 PC7 is connected with FMC_NE1 signal when JP10 is fitted