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PulseBlasterESR-PRO-II
II. Product Description and Specifications
Device Architecture
Figure 2 presents the general architecture of the PulseBlasterESR-PRO-II system. The major building
blocks are the SRAM memory, the Control Unit, and the Phase-locked Loop (PLL). The entire logic design,
including the SRAM memory, is contained on a single FPGA chip (System-on-a-Chip design).
Operation
The PulseBlasterESR-PRO-II uses a control unit and memory to send pulses to the output lines. The
SRAM memory for the 250MHz model can contain up to 8k output words for the 24-channel model. Each
channel can be programmed individually (see the example C program in Section V). Not all memory locations
need to be be programmed. The pulse sequence can be varied as desired as long as it fits inside the
device's capabilities.
When the PulseBlasterESR-PRO-II is programmed and triggered, it will step through each memory
location and output the desired pulse sequence. Once the last programmed memory location has been
reached, the device will loop back to the start of the pulse sequence.
Output signals
The PulseBlasterESR-PRO-II allows up to 24 output channels to be configured. All output signals are
routed to the pins of the IDC on-board connector. Additionally, the first 4 output signals are routed to four
bracket mounted BNC connectors (see Section III for more information). The BNC connector outputs
have impedance matched to 50 ohms.
The output channels comply with the 3.3V TTL-level standard, and are capable of delivering ±25 mA
per channel. If more output current is necessary, please contact SpinCore Technologies, Inc.
2016/08/17
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Figure 2:
General PulseBlasterESR-PRO-II board architecture. This is all implemented on a
single FPGA, making this device a System-on-a-Chip design. The clock oscillator signal is
derived from an on-chip PLL circuit typically using a 50 MHz on-board reference clock.
Control Unit
SRAM
Memory
PLL
PCI Bus
TTL Clock
Data
Control
Output
FPGA
