Spectrum M2p.59 Series, Руководство по оборудованию, Страница: 148 / 190

148 (c) Spectrum Instrumentation GmbH
Programming examples Mode Gated Sampling
High level hysteresis trigger
.This trigger mode will generate an internal gate signal that
can be useful for masking a second trigger event generated
by a different mode. The analog input is continuously sam -
pled with the selected sample rate.
If the signal is equal or higher than the programmed trigger
level the gate starts.
When the signal is lower than the programmed hysteresis lev -
el the gate will stop.
As this mode is level-triggered, the high level at the cards start
time does trigger the board.
Low level hysteresis trigger
.This trigger mode will generate an internal gate signal that
can be useful for masking a second trigger event generated
by a different mode. The analog input is continuously sam -
pled with the selected sample rate.
If the signal is equal or lower than the programmed trigger
level the gate starts.
When the signal is higher than the programmed hysteresis
level the gate will stop.
As this mode is level-triggered, the high level at the cards start
time does trigger the board.
Programming examples
The following examples shows how to set up the card for Gated Sampling in standard mode and for Gated Sampling in FIFO mode.
Register Value Direction set to Value
SPC_TRIG_CH0_MODE 40610 read/write SPC_TM_HIGH | SPC_TM_HYSTERESIS 20000008h
SPC_TRIG_CH0_LEVEL0 42200 read/write Set it to the desired trigger level relatively to the channel’s input range. board dependant
SPC_TRIG_CH0_LEVEL1 42300 read/write Defines the hysteresis level relatively to the channel’s input range board dependant
Register Value Direction set to Value
SPC_TRIG_CH0_MODE 40610 read/write SPC_TM_LOW | SPC_TM_HYSTERESIS 20000010h
SPC_TRIG_CH0_LEVEL0 42200 read/write Set it to the desired trigger level relatively to the channel’s input range. board dependant
SPC_TRIG_CH0_LEVEL1 42300 read/write Defines the hysteresis level relatively to the channel’s input range board dependant
spcm_dwSetParam_i32 (hDrv, SPC_CARDMODE, SPC_REC_STD_GATE); // Enables Standard Gated Sampling
spcm_dwSetParam_i32 (hDrv, PRETRIGGER, 256); // Set the pretrigger to 256 samples
spcm_dwSetParam_i32 (hDrv, POSTTRIGGER, 2048); // Set the posttrigger to 2048 samples
spcm_dwSetParam_i32 (hDrv, SPC_MEMSIZE, 8192); // Set the total memsize for recording to 8192 samples
spcm_dwSetParam_i32 (hDrv, SPC_TRIG_EXT0_MODE, SPC_TM_POS); // Set triggermode to ext. TTL mode (rising edge)
spcm_dwSetParam_i32 (hDrv, SPC_TRIG_EXT0_LEVEL0, 1500); // Set trigger level to +1500 mV
spcm_dwSetParam_i32 (hDrv, SPC_TRIG_ORMASK, SPC_TMASK_EXT0); // and enable it within the trigger OR-mask
spcm_dwSetParam_i32 (hDrv, SPC_CARDMODE, SPC_REC_FIFO_GATE); // Enables FIFO Gated Sampling
spcm_dwSetParam_i32 (hDrv, PRETRIGGER, 128); // Set the pretrigger to 128 samples
spcm_dwSetParam_i32 (hDrv, POSTTRIGGER, 512); // Set the posttrigger to 512 samples
spcm_dwSetParam_i32 (hDrv, SPC_LOOP, 1024); // 1024 gates will be recorded
spcm_dwSetParam_i32 (hDrv, SPC_TRIG_EXT0_MODE, SPC_TM_NEG); // Set triggermode to ext. TTL mode (falling edge)
spcm_dwSetParam_i32 (hDrv, SPC_TRIG_EXT0_LEVEL0, -1500); // Set trigger level to -1500 mV
spcm_dwSetParam_i32 (hDrv, SPC_TRIG_ORMASK, SPC_TMASK_EXT0); // and enable it within the trigger OR-mask