Sony Tektronix AWG2021, Руководство по обслуживанию

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AWG2021 Service Manual
3-1
Theory of Operation
This section describes the basic operation of the major circuit blocks or modules
in the AWG2021. Section 9, Diagrams, includes three block diagrams and two
interconnect diagrams. Figures 9–1, 9–2, and 9–3 show the modules and
functional blocks of the AWG2021 with Options 02 , 03, 04, and 09 installed.
Figures 9–4 and 9–5 show how the modules interconnect.
Module Overview
The module overview describes the basic operation of each functional circuit
block.
The AWG2021 Arbitrary Waveform Generator is a portable, single- or dual-
channel instrument. For each channel, the AWG2021 reads the digital waveform
data loaded into its waveform memory. The point rate clock determines the rate
at which the data is read. The AWG2021 converts the data from digital to analog
format and outputs the resulting arbitrary waveform.
The clock synthesizer circuit is a PLL oscillator that uses a 12.8 MHz reference
crystal. It supplies a point rate clock that is adjustable from 250 MHz to 10 Hz
for reading data from CH1 waveform memory. The point rate clock is also
divided and used for reading data from Option 02 CH2 waveform memory.
When an external clock source is selected, the external clock signal is passed
directly through to the Control board and used for reading waveform data in
memory. With Option 02 installed, the CH2 clock divider divides the external
clock source based on the selected ratio, thus allowing CH 2 to vary its clock
rate.
The clock divider circuit divides the clock signal from the Synthesizer board.
The resulting clock is the point rate clock used for reading waveform data from
the CH1 or CH2 waveform memory.
This waveform memory control block controls the waveform memory addresses
read out according to the contents of a sequence file.
This functional block contains the memory that holds the waveform digital data.
The memory is divided into eight banks; its output is multiplexed. There are 12
bits for waveform data and two bits for waveform markers (for each channel).
Clock Synthesizer (A10,
Synthesizer Board)
CH1/CH2 Clock Divider
(A21/A31, Control Board)
Waveform Memory
Control (A21, Control
Board)
Waveform Memory (A2,
Memory Board)