STR-DA5500ES
138
Pin No.
Pin Name
I/O
Description
1
RDATA0
I
Digital audio signal input from the digital audio interface receiver or HDMI receiver
2 to 8
-
-
Not used
9
DSP2_SIB_SEL
O
Data selection signal output to the data selector
10
P_ERROR
I
PLL lock error signal and data error
fl
ag input from the DSP1
11
DSP1_SPIDS
O
Serial data latch pulse signal output to the DSP1
12
DSP1_RESET
O
Reset signal output to the DSP1 and
fl
ash memory “L”: reset
13, 14
DSP1_BOOTCFG0,
DSP1_BOOTCFG1
O
Boot mode setting signal output to the DSP1
15, 16
-
-
Not used
17
SF2_DSP2_MAS
I
Master/slave mode selection signal input from the DSP2
18, 19
-
-
Not used
20
SF2_CPU_CE
O
Chip enable signal output to the serial
fl
ash
21
DSP2_SPIDS
O
Serial data latch pulse signal output to the DSP2
22
DSP2_RESET
O
Reset signal output to the DSP2 "L": reset
23, 24
-
-
Not used
25, 26
DSP2_BOOTCFG0,
DSP2_BOOTCFG1
O
Boot mode setting signal output to the DSP2
27 to 35
-
-
Not used
36
DRST_TRG
O
Programming end
fl
ag output to the system controller “H”: end
37 to 39
-
-
Not used
40
VSS
-
Ground terminal
41
SDA
I/O
Two-way I2C data bus with the system controller
42
SCL
I/O
Two-way I2C clock bus with the system controller
43
VSS
-
Ground terminal
44
VCC
-
Power supply terminal (+3.3V)
45 to 47
-
-
Not used
48
RD
O
Read strobe signal output terminal Not used
49
WR0
O
Write strobe signal output terminal Not used
50, 51
-
-
Not used
52
MD2
I
Programming mode setting signal input from the system controller
53, 54
MD1, MD0
I
Programming mode setting signal input terminal Not used
55
XRESET
I
Reset signal input from the system controller “L”: reset
56
VCC
-
Power supply terminal (+3.3V)
57
XOUT
O
System clock output terminal (12.5 MHz)
58
XIN
I
System clock input terminal (12.5 MHz)
59
VSS
-
Ground terminal
Not used
Busy signal input from the system controller “H”: busy
Busy signal output to the system controller “H”: busy
Interrupt signal output terminal Not used
Not used
Not used
Not used
Ground terminal
Power supply terminal (+3.3V)
Not used
81
INT0
I
Interrupt signal input terminal Not used
82
MD_INT
I
Interrupt signal input from the system controller
83
DSP1_INT
I
Interrupt signal input from the DSP1
84
DSP2_INT
I
Interrupt signal input from the DSP2
85, 86
INT4, INT5
I
Interrupt signal input terminal Not used
87, 88
-
-
Not used
89
MD_DATA
I
Serial data input terminal Not used
90
DM_DATA
O
Serial data output terminal Not used
91
SCK0
O
Serial data transfer clock signal output terminal Not used
DSP BOARD IC5208 MB91F353APMT-GE1 (DSP CONTROLLER)
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TEL 13942296513 QQ 376315150 892498299
