52
HCD-CZ1/NAS-CZ1
MAIN BOARD IC601
µ
PD703261YGF-S06-JBT-A (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Pin Description
1
MODEL
I
Setting terminal for model discrimination
2
DEST
I
Setting terminal for the destination
3
AVREF0
I
Reference voltage (+3.3V) input terminal
4
AVSS
-
Ground terminal
5
NO_USE1
O
Not used
6
SOFT-CHECK
O
Soft check terminal
7
AVREF1
I
Reference voltage (+3.3V) input terminal
8
STBY_LED
O
Standby LED drive signal output terminal
9
NO_USE2
O
Not used
10
FLASH0
I
Internal flash memory data write control signal input terminal
11
VDD
-
Power supply terminal (+3.3V)
12
REGC
-
Regulator control terminal
13
VSS
-
Ground terminal
14
X1
I
Main system clock input terminal (5 MHz)
15
X2
O
Main system clock output terminal (5 MHz)
16
RESET
I
System reset signal input from the reset signal generator
17
XT1
I
Sub system clock input terminal Not used
18
XT2
O
Sub system clock output terminal Not used
19
SELF_PROG
O
For self programming terminal Normally not used
20
KEY_INT
I
System wake up signal input by key input
21
RM_INT
I
System wake up signal input by SIRCS input
22
(CAN’T USE)
I
Not used
23
AC_CUT
I
AC off detection signal input terminal “L”: AC off
24
FLASH_DI
I
Internal flash memory data writing signal input terminal Normally not used
25
FLASH_DO
O
Internal flash memory data reading signal output terminal Normally not used
26
FLASH_CLK
O
Clock signal output for internal flash memory data writing Normally not used
27
FL_DATA
O
Serial data output to the fluorescent display tube driver
28
SIRCS
I
SIRCS signal input terminal
29
FL_CLK
O
Serial data transfer clock signal output to the fluorescent display tube driver
30
FL_CS
O
Chip select signal output to the fluorescent display tube driver
31
FL_RESET
O
System reset signal output to the fluorescent display tube driver
32
HP_IN
I
Detection input for headphone plug
33
AMP_MUTING
O
Muting signal output to the power amplifier
34
AMP_STBY
O
Standby on/off control signal output to the power amplifier
35
EVSS
-
Ground terminal
-
Power supply terminal (+3.3V)
I/O
I2C two-way data bus with the EEPROM
I/O
I2C data transfer clock signal input and output
O
LED drive signal output terminal
O
Not used
O
Speaker relay drive signal output terminal
O
Power on/off relay drive signal output terminal
O
Headphone muting on/off control signal output terminal
O
Line muting on/off control signal output terminal
O
Serial data transfer clock signal output to the electrical volume
46
GEQ_DATA
O
Serial data output to the electrical volume
47
LED6
O
LED drive signal output terminal Not used
48 to 51
NO_USE5 to NO_USE8
O
Not used
52
I-SENS
I
Internal status (SENSE) input from the CD DSP
53
O-DATA
O
Serial data output to the CD DSP
54
O-CLOCK
O
Serial data transfer clock signal output to the CD DSP
55
I-MP3DATA
I
Serial data input from the CD DSP
56
O-MP3DATA
O
Serial data output to the MP3 decoder
57
O-MP3CLK
O
Serial data transfer clock signal output to the MP3 decoder
58
I-SCOR
I
Subcode Q sync (SCOR) input from the CD DSP
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