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MHC-V7D
68
• IC Pin Function Descriptions
MOTHERBOARD BOARD (8/8) IC101 R7S7200032CFP-A (SYSTEM CONTROL)
Pin No.
Pin Name
I/O
Description
1
SRC-RST0
O
Not used
2
VIDEO-MUTE
O
Muting Control for Video
3
CDM-UNLOAD-SW
I
CDM Open
4
CDM-LOAD-SW
I
CDM Close
5
BT-RESET
O
Reset signal output to Bluetooth section
6
AC Supply Low Det
I
AC Supply Low voltage Detection
7
Vcc
-
Power supply terminal (+3.3V)
8
BT-ON
O
Bluetooth on/off control signal output terminal for bluetooth section
9
Vss
-
Ground terminal
10
FL_OSC
O
FL FRAME RATE EXT CLOCK
11
PVcc
-
Power supply terminal (+3.3V)
12
NFC INT
I
NFC interrupt
13
MTK-POWER-CTRL
O
Power Control pin for MTK
14
AUDIO_CLK_OUT
O
Clock Signal from Aragon to MTK master clock
15
MTK-RESET
O
MTK Reset pin
16
MTK-BUSY
O
BUSY Signal communication between MTK
17
MTK-CLK
I
Clock Signal from MTK
18
Vss
-
Ground terminal
19
MTK-XIFCS
I
MTK Chip select
20
MTK-SDI
I
Data In Signal from MTK
21
Vcc
-
Power supply terminal (+3.3V)
22
MTK-SDO
O
Data Out Signal to MTK
23
Vss
-
Ground terminal
24
SSI3_BCKO
I
Bit clock signal from MTK to Aragon
25
PVcc
-
Power supply terminal (+3.3V)
26
SSI3_LRCKO
I
LR clock signal from MTK to Aragon
27
C-CONT
O
Trigger port to start charging of SPM
28
SSI3_DI
I
SRC from MTK to Aragon data in
29
SSI0_BCKO
O
Clock signal from Aragon to Wf DAC BCK
30
SSI0_LRCKO
O
Clock signal from Aragon to Wf DAC LRCK
31
Vss
-
Ground terminal
32
SSI0_DO
O
Data Out from Aragon to Wf DAC
33
SSI2_DO
O
Data Out from Aragon to AUX OUT DAC
34
Vcc
-
Power supply terminal (+3.3V)
35
LCD_CLK
O
Serial clock output to FL CIG
36
Vss
-
Ground terminal
37
CKIO
-
Not used
38
LCD_CSB
O
LCD Chip Select
39
PVcc
-
Power supply terminal (+3.3V)
40
LCD-SDA
O
Serial data output to LCD
41
ANALOG-ASEL
O
Multiplexer selector A for Analog input
42
ANALOG-BSEL
O
Multiplexer selector B for Analog input
43
DEBUG-TxD
O
TxD (for Debug)
44
JOG+
I
File search JOG positive
45
POWER-KEY
I
Power Key input terminal
46
Vss
-
Ground terminal
47
USB-OC
I
USB Overcurrent Detection input port
48
RGB-SOUT
O
Serial data output to RGB driver
49
JOG-
I
File search JOG negative
50
PVcc
-
Power supply terminal (+3.3V)
51
LINK-OUT-B
O
Selector B for Party Chain Signal
52
VBUS-OE
O
MTK Vbus Output enable control pin
53
NFC-RF-DET
I
NFC RF signal detection signal input from the NFC section
54
SSI1_DO
O
Data Out signal from Aragon to SWF DAC
Содержание MHC-V7D
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