Sony HDVF-C35W, Руководство по обслуживанию

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HDVF-C35W
PR-309 (5/5)
SUFFIX: -11, 12
PR-309 (5/5)
SUFFIX: -11, 12
PR-309 (5/5)
BOARD NO. 1-873-970-11, 12
HD_LCD
VD_LCD
Y_LCD[0]
PCLK_LCD
C_LCD[3]
C_LCD[7]
C_LCD[8]
C_LCD[9]
Y_LCD[1]
Y_LCD[2]
Y_LCD[3]
Y_LCD[4]
Y_LCD[6]
Y_LCD[5]
Y_LCD[7]
Y_LCD[8]
Y_LCD[9]
C_LCD[0]
C_LCD[1]
C_LCD[6]
C_LCD[2]
C_LCD[4]
C_LCD[5]
HD_LCD
TP402
VD_LCD
TP401
GND
G2
10
G1
9
OUT4
8
IN4
7
OUT3
6
IN3
5
OUT2
4
IN2
3
OUT1
2
IN1
1
FL406
EMI
GND
R404
0
R405
0
GND
SUFFIX -12: C407 22pF
SUFFIX -11: R403 22pF
002
FPGA_SDA_I2C
002 FPGA_SCL_I2C
51 50 49 48 47 46 45 44 43 42 41
NC 40
VDD1 39
GND2 38
GND2 37
VDD2 36
VDD2 35
NC 34
GND1 33
GND1 32
VDD1 31
VDD1 30
I_CAM_AU_SCS 29
O_LCD_SRX 28
I_LCD_SCS 27
I_EVF_STX 26
I_EVF_SCLK 25
I_LCD_XRST 24
I_LCD_VD 23
I_LCD_HD 22
I_LCD_CLK 21
I_LCD_Y0 20
I_LCD_Y1 19
I_LCD_Y2 18
I_LCD_Y3 17
I_LCD_Y4 16
I_LCD_Y5 15
I_LCD_Y6 14
I_LCD_Y7 13
I_LCD_Y8 12
I_LCD_Y9 11
I_LCD_C0 10
I_LCD_C1 9
I_LCD_C2 8
I_LCD_C3 7
I_LCD_C4 6
I_LCD_C5 5
I_LCD_C6 4
I_LCD_C7 3
I_LCD_C8 2
I_LCD_C9 1
CN5
GND
R402
0
NM
R401
0
NM
R400
0
C404
1uF
C403
0.1uF
C405
0.1uF
C406
1uF
C402
1uF
C401
0.1uF
D402
SLI-343URCT32WST
D401
SLI-343URCT32WST
002 CPU_INT
GND
G2
10
G1
9
OUT4
8
IN4
7
OUT3
6
IN3
5
OUT2
4
IN2
3
OUT1
2
IN1
1
FL407
EMI
GND
GND
GND
GND
GND
GND
G2
10
G1
9
OUT4
8
IN4
7
OUT3
6
IN3
5
OUT2
4
IN2
3
OUT1
2
IN1
1
FL403
EMI
G2
10
G1
9
OUT4
8
IN4
7
OUT3
6
IN3
5
OUT2
4
IN2
3
OUT1
2
IN1
1
FL401
EMI
G2
10
G1
9
OUT4
8
IN4
7
OUT3
6
IN3
5
OUT2
4
IN2
3
OUT1
2
IN1
1
FL400
EMI
G2
10
G1
9
OUT4
8
IN4
7
OUT3
6
IN3
5
OUT2
4
IN2
3
OUT1
2
IN1
1
FL405
EMI
G2
10
G1
9
OUT4
8
IN4
7
OUT3
6
IN3
5
OUT2
4
IN2
3
OUT1
2
IN1
1
FL404
EMI
G2
10
G1
9
OUT4
8
IN4
7
OUT3
6
IN3
5
OUT2
4
IN2
3
OUT1
2
IN1
1
FL402
EMI
JC401
0
GND
C400
0.1uF
+3.3V
GND
1
G
2
INA
3
GND
4
OUTY
5
VCC
IC400
TC7SZ125FU(TE85R)
002 EPR2_nCE
002 EPR2_CONFIG_DONE
002 EPR2_nCS
002 EPR2_DCLK
002 EPR2_nCONFIG
002 EPR2_DATAOUT
002 EPR2_ASDI
GND
GND
GND
GND
GND
GND
GND
GND
002 FPGA_LCD
002,003,005 SPI_STD
GND
002 V_SYNC_SEP
GND
005 CS_LCD
44 43 42 41
- 40
- 39
Pr(G) 38
Pr(X) 37
Pb(G) 36
Pb(X) 35
Y(G) 34
Y(X) 33
GND 32
GND 31
+1.8V(A/D) 30
+1.8V(A/D) 29
GND 28
GND 27
+3.3V(A/D) 26
+3.3V(A/D) 25
GND 24
GND 23
+1.5V 22
+1.5V 21
GND 20
GND 19
+1.8V(IP) 18
+1.8V(IP) 17
GND 16
GND 15
+3.3V 14
+3.3V 13
GND 12
GND 11
+3.0V 10
+3.0V 9
GND 8
GND 7
+5V(TALLY) 6
GND 5
+5V(BL) 4
+5V(BL) 3
GND 2
GND 1
CN3
001 Pb(X)
002
V_SYNC
002 LCD_RESET
002 CPU_RESET
001,002 3.3V_SDA_I2C
005 SPI_STD
002 SPI_SCLK
002 CS_OSD
005 CS_LCD
+3.3V
002 H_SYNC_SEP
+1.8V_IP
003
CS_IP
+5.0V_TALLY
+1.5V
+5.0V_BL
+3.3V_A/D
+1.8V_A/D
001
Y(X)
005 CS_CPLD
GND
+3.0V
002
O/E_FIELD_SEP
002,003,005 SPI_SRD
34 33 32 31
GND 30
CPU_CLOCK 29
CPU_RESET 28
O/E(SEP) 27
V SYNC(SEP) 26
H SYNC(SEP) 25
SCK(3.3V) 24
SDA(3.3V) 23
SRX 22
STX 21
SCK 20
CS5(LCD) 19
CS4(LCD_FPGA) 18
CS3(OSD) 17
CS2(iChips) 16
CS1(FPGA) 15
UP TALLY 14
V SYNC 13
H SYNC 12
DATA0 11
DCLK 10
ASDO 9
nCSO 8
nCE 7
nCONFIG 6
CONFIG_DONE 5
CPU_INT 4
FPGA_SCL(3.3V) 3
FPGA_SDA(3.3V) 2
SCK 1
CN4
002 H_SYNC
005 CS_CPLD
+3.0V
001 Pr(X)
+5.0V_BL
005
SPI_SRD
GND
002 CPU_CLOCK
GND
001,002
3.3V_SCL_I2C
002 CS_FPGA
R408 0
R412 0
SUFFIX -12