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6-1
6-1
HDVF-C35W
Overall
Overall
Section 6
Block Diagrams
Overall
IC300, IC301
MEMORY
: Back Light/TALLY
: LCD/FPGA
SDRAM 32bit
x
2
: SCALER/FPGA/ADC
: FPGA
77MHz
x
1.875
: ANA
64
12
2
MCLK_77M
IC200
DATA
ADRS
CTRL
IC107
1.15MHz
2
4
LCD PANEL MODULE
Pr
CHAR
GEN
LPF
IC1
IC100 (1/2)
IC100-IC103
IC200-IC203
IC300-IC303
DISPLAY PROCESSOR
2 CHAR
CS_OSD
SPI_SCLK
SPI_STD
SPI_SRD
OSDDT
CHAR BACK
Pb
OSDEN
LPF
AD
CONVERTER
30
(POHS)
IC100(2/2)
IF-1070
PR-308
PR-309
RE-249 (1/2)
LCD BLOCK
LCD PANEL
PI2VS
PI2HS
PI2FLD
PI2ACT
3
Y
R_IN_(0)-(9)
G_IN_(0)-(9)
B_IN_(0)-(9)
30
FPGA
Y_LCD(0)-(9)
C_LCD(0)-(9)
10
YUV_IN
VF
LPF
SCL
IN2_D(0)-D(29)
A/D FPGA
SDA
FPGA_SDA_I2C
4
10
3
PEAKING
SYNC
SEP
3
KNEE
FPGA
74MHz
PICLK
CRISP
H_SYNC(SEP),
V_SYNK(SEP),
O/E_FIELD(SEP)
IC103
RGB
→
YC
PCLK_LCD
IC6
IPCLKx1.33
CHAR MIX
HD_LCD
VD_LCD
IC409
IND MIX
33.2MHz
IC408
SDA_I2C
SCL_I2C
FPGA_SCL_I2C
74M
FREQUENCY
DIVIDED
MAKE DE SIGNAL
ADJUST PHASE
BETWEEN HD/VD
EEPROM
POCLK
18MHz
FPCG
33.2MHz
MCLK_77M
331kHz
SCLK
VCO AND PHASE
FREQUENCY
DETECTOR
POCLK_33.2M
400kHz
ADJUST PHASE
CLK
POHS
POVS
POACT
SCL
IC101
SDA
SPI_STD
SPI_SCLK
CS_iChips
SCLK
IC411
IC602
IC603
IC600
IC601(1/2)
IC601(2/2)
ROM
4.64MHz
RESET
IC106
BACK LIGHT
18.5M
SPI_STD
SPI_SCLK
CS_FPGA
9.25M
RESET
CPU_CLK
3LINE BUS CONTROL
6
CS_CPLD
SPI_SRD
CP_LCD
SPI_STD
SPI_SCLK
LCD_RESET
RED_TALLY_IN
SCL
GREEN_TALLY_IN
SDA
SW
SW
CPU
IC400
IC201
SPI_STD
SPI_SCLK
CS_LED_DRIVER
CPU CLK:18.5MHz
S400
2
4bit DIP SW
SW-1366
RE-249 (2/2)
ASSIGN 1
LED
DRIVER
S401
8bit DIP SW
2
2
2
ASSIGN 2
4
ADC
SECOND VF
8bit
CONTRAST
PEAKING
MIRROR_SW
35
S1
S2
S3
process
EEPROM
BRIGHT
1
RV3
S1
S2
1
RV2
1
RV1
LEVEL SHIFTING
HOT SWAPPABLE
2-WIRE BUS BUFFER
WITH ENABLE
Q1
UNREG
UNREG
IC5
Q18, L2
H_START_UP
Q19, L4
Q2
Q7
IC6
Q24, L6
Q5, Q6
Q25, L7
IC2
IC1
IC4
IC7
H_SHUTDOWN
DC/DC
CONTOROL
DC/DC
CONTOROL
SWITCHING
CONVERTER
SWITCHING
CONVERTER
SWITCHING
CONVERTER
SWITCHING
CONVERTER
DOWN
DETECT
SHUNT
REG
OP AMP
+
5.0V
+
1.8V
+
3.3V
+
1.5V
_
3.3V
REG
_
3.3V
LE-341
G_TALLY
R_TALLY
BATT
LE-342
!
MAG
R_TALLY
X_TALLY
SAVE
MIRROR_SW
+
5.0V
+
1.8V
+
3.3V
_
3.3V
+
1.5V
X1
28.63636MHz
X100
74.250MHz
2
2
4
7
MKR
ZEBRA
TALLY
: ANA/ADC/SCALER/FPGA/SDRAM/uCOM
2
2
S4
MENU
S3
ENT
.
.
.
.
.
.
+
5V
+
3.3V
+
3V
+
1.8V
+
1.5V
_
3.3V
Содержание HDVF-C35W
Страница 4: ...2 E HDVF C35W 8 Board Layouts LE 341 8 1 LE 342 8 1 PR 308 8 2 PR 309 8 3 RE 249 8 4 SW 1366 8 4 ...
Страница 6: ......
Страница 22: ......
Страница 42: ......
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Страница 61: ......
Страница 62: ...Printed in Japan Sony Corporation 2007 6 22 2007 HDVF C35W SY J E 9 968 349 01 ...