SN8P2318 Series
C-type LCD, RFC 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 95
Version 1.5
Event Counter Trigger Format
The capture timer input source has high pulse, low pulse and cycle signal. In event counter function, the trigger format
is not like capture timer and fixed rising edge format. Use the start trigger signal of capture timer to be the event
counter trigger source:
n+1
n
n+2
n+3
n+4
n+5
Input Signal
10-bit Event Counter
8.4.8 T1VCH, T1VCL 10-bit EVENT COUNTER REGISTERS
T1 event counter is 10-bit counter combined with T1VCH and T1VCL registers. When T1 event counter overflow
occurs, the T1IRQ flag is set
as “1” and cleared by program. The T1VCH, T1VCL decide T1 event counter number.
0A3H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T1VCL
T1VCL7
T1VCL6
T1VCL5
T1VCL4
T1VCL3
T1VCL2
T1VCL1
T1VCL0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
0A4H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T1VCH
-
-
-
-
-
-
T1VCH1
T1VCH0
Read/Write
-
-
-
-
-
-
R/W
R/W
After Reset
-
-
-
-
-
-
0
0
The T1 event counter length is 10-bit and points to T1VCH and T1VCL registers. The core bus is 8-bit, so access 10-bit
data needs a latch flag to avoid the transient status affect the 10-bit data mistake occurrence. Under write mode, the
write T1VCH is the latch control flag. Under read mode, the read T1VCL is the latch control flag. So, write T1 10-bit
event counter is to write T1VCH first, and then write T1VCL. The 10-bit data is written to 10-bit counter buffer after
executing writing T1VCL. Read T1 10-bit event counter is to read T1VCL first, and then read T1VCH. The 10-bit data is
dumped to T1VCH, T1VCL registers after executing reading T1VCL.
Read T1 event counter buffer sequence is to read T1VCL first, and then read T1VCH.
Write T1 event counter buffer sequence is to write T1VCH first, and then write T1VCL.
