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SN8P1829

8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Reg 128 dots LCD driver

SONiX TECHNOLOGY CO., LTD

Page 37

Version 1.0

BITS of SYSTEM REGISTER

Address

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W

Name

080H LBIT7 LBIT6 LBIT5 LBIT4 LBIT3

LBIT2

LBIT1

LBIT0

R/W

081H HBIT7 HBIT6 HBIT5 HBIT4 HBIT3

HBIT2

HBIT1

HBIT0

R/W H

082H RBIT7 RBIT6 RBIT5 RBIT4 RBIT3

RBIT2

RBIT1

RBIT0

R/W R

083H ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3

ZBIT2

ZBIT1

ZBIT0

R/W

084H YBIT7 YBIT6 YBIT5 YBIT4 YBIT3

YBIT2

YBIT1

YBIT0

R/W Y

085H XBIT7 XBIT6 XBIT5 XBIT4 XBIT3

XBIT2

XBIT1

XBIT0

R/W X

086H

NT0

NPD

- - - C

R/W

PFLAG

087H

- - - -

RBNKS3 RBNKS2 RBNKS1 RBNKS0

R/W RBANK

088H

- - - -

RTCM1 RTCM0

RCLK

R/W

OPTION

089H - -

LCDBNK

LCDENB

BIAS P2SEG

R/W

LCDM1

092H

PGIACKS7 PGIACKS6 PGIACKS5 PGIACKS4

PGIACKS3

PGIACKS2

PGIACKS1

PGIACKS0

R/W PGIACKS

095H

- - - -

CPSTS

CPAUTO

CPON

CPRENB

R/W CPM

096H

CPCKS7 CPCKS6 CPCKS5 CPCKS4 CPCKS3 CPCKS2 CPCKS1

CPCKS0 R/W CPCKS

09AH P2GS3 P2GS2 P2GS1 P2GS0

P1GS1

P1GS0

PGIAENB

R/W PGIAM

09BH

- - - - - -

OP2ENB OP1ENB

R/W OPM

0B1H ADENB ADS EOC GCHS

CHS1

CHS0

R/W

ADM

0B2H ADB11

ADB10 ADB9 ADB8 ADB7

ADB6

ADB5

ADB4

R ADB

0B3H -

ADCKS1

ADLEB

ADCKS0

ADB3

ADB2

ADB1

ADB0

R/W ADR

0B4H SENB

START

SRATE1

SRATE0

SIG SCKMD SEDGE

TXRX

R/W

SIOM

0B5H SIOR7 SIOR6 SIOR5 SIOR4 SIOR3

SIOR2

SIOR1

SIOR0

W SIOR

0B6H SIOB7 SIOB6 SIOB5 SIOB4 SIOB3

SIOB2

SIOB1

SIOB0

R/W SIOB

0BFH

PEDGEN

- -

P00G1

P00G0

- - -

R/W

PEDGE

0C0H

- - - -

P13W

P12W

P11W

P10W

P1W

0C1H

- - - -

P13M

P12M

P11M

P10M

R/W

P1M

0C5H

- - -

P54M

P53M

P52M

P51M

P50M

R/W

P5M

0C8H -

TC1IRQ

TC0IRQ

T0IRQ

SIOIRQ

- P01IRQ P00IRQ

R/W

INTRQ

0C9H -

TC1IEN

TC0IEN

T0IEN

SIOEN

- P01IEN

P00IEN

R/W

INTEN

0CAH WTCKS

WDRST

WDARTE

CPUM1 CPUM0 CLKMD STPHX

- R/W

OSCM

0CDH TC0R7 TC0R6 TC0R5 TC0R4 TC0R3

TC0R2

TC0R1

TC0R0

W TC0R

0CEH PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 R/W

PCL

0CFH

- - -

PC12

PC11

PC10

PC9

PC8

R/W

PCH

0D0H

- - - - - -

P01

P00

0D1H

- - - -

P13

P12

P11

P10

R/W

0D2H P27 P26 P25 P24 P23 P22 P21 P20 R

0D5H

- - -

P54

P53

P52

P51

P50

R/W

0D8H T0ENB

T0RATE2 T0RATE1

T0RATE0

TC1X8

TC0X8

TC0GN

T0TB R/W

T0M

0D9H T0C7 T0C6 T0C5 T0C4 T0C3

T0C2

T0C1

T0C0 R/W

T0C

0DAH TC0ENB

TC0RATE2 TC0RATE1 TC0RATE0

TC0CKS ALOAD0

TC0OUT

PWM0OUT

R/W TC0M

0DBH TC0C7 TC0C6 TC0C5 TC0C4 TC0C3

TC0C2

TC0C1

TC0C0

R/W TC0C

0DCH TC1ENB

TC1RATE2 TC1RATE1

TC1RATE0

TC1CKS ALOAD1

TC1OU

PWM1OUT

R/W TC1M

0DDH TC1C7 TC1C6 TC1C5 TC1C4 TC1C3

TC1C2

TC1C1

TC1C0

R/W TC1C

0DEH TC1R7 TC1R6 TC1R5 TC1R4 TC1R3

TC1R2

TC1R1

TC1R0

W TC1R

0DFH

GIE

- - -

STKPB3 STKPB2 STKPB1 STKPB0

R/W

STKP

0E0H

- - - - - -

P01R

P00R

P0UR

0E1H

- - - -

P13R

P12R

P11R

P10R

P1UR

0E2H P27R P26R P25R P24R P23R

P22R

P21R

P20R W P2UR

0E5H

- - -

P54R

P53R

P52R

P51R

P50R

P5UR

0E6H @HL7 @HL6 @HL5 @HL4 @HL3

@HL2

@HL1

@HL0

R/W @HL

0E7H @YZ7 @YZ6 @YZ5 @YZ4 @YZ3

@YZ2

@YZ1

@YZ0

R/W @YZ

(To be continued)

Содержание SN8P1829

Страница 1: ...authorized for us as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of t...

Страница 2: ...dd P0 1 description 5 Pin assignment V1 V2 V3 re arrange 6 Application circuit VLCD power came from AVDDR VDD Pre V0 3 Jul 2003 1 Change the minimal different voltage between AVREFH and AVREFL form 1...

Страница 3: ...RY 2 1 1 1 PRODUCT OVERVIEW 7 FEATURES 7 FEATURES TABLE 7 SYSTEM BLOCK DIAGRAM 8 PIN ASSIGNMENT 9 PIN DESCRIPTIONS 10 PIN CIRCUIT DIAGRAMS 11 2 2 2 CODE OPTION TABLE 12 3 3 3 ADDRESS SPACES 13 PROGRAM...

Страница 4: ...6 POWER ON RESET 39 OVERVIEW 39 EXTERNAL RESET DESCRIPTION 40 LOW VOLTAGE DETECTOR LVD DESCRIPTION 41 7 7 7 OSCILLATORS 42 OVERVIEW 42 SYSTEM MODE DESCRIPTION 48 SYSTEM MODE CONTROL 49 WAKEUP TIME 51...

Страница 5: ...DATA BUFFER 94 SIOR REGISTER DESCRIPTION 94 SIO MASTER OPERATING DESCRIPTION 95 SIO SLAVE OPERATING DESCRIPTION 99 SIO INTERRUPT OPERATION DESCRIPTION 104 1 1 11 1 1 I O PORT 105 OVERVIEW 105 I O POR...

Страница 6: ...OPA 119 OVERVIEW 119 BLOCK DIAGRAM 119 VOLTAGE CHARGE PUMP REGULATOR CPR 120 PROGRAMMABLE GAIN INSTRUMENTATION AMPLIFIER PGIA 123 OPA OPERATIONAL AMPLIFIER 125 1 1 15 5 5 APPLICATION CIRCUIT 126 BLOOD...

Страница 7: ...ns are 1 cycle only Maximum instruction cycle is 2 JMP instruction jumps to all ROM area All ROM area look up table function MOVC Support hardware multiplier MUL Single power supply 2 4V 5 5V Built in...

Страница 8: ...ROL TIMER COUNTER PORT 0 PORT 1 PORT 2 PORT 5 SEG COM FLAGS ADC AIN0 AIN2 L OSC SIO TX RX PWM0 PWM1 PWM0 Buzzer0 PWM1 Buzzer1 Charge Pump AVDDCP PGIA PGIAOUT PGIAIN PGIAIN AVDDR PC IR OTP ROM H OSC TI...

Страница 9: ...G10 AVREFL 4 57 SEG11 AIN2 5 56 SEG12 AIN1 6 55 SEG13 AIN0 7 54 SEG14 AVREFH 8 53 SEG15 PGIABIAS 9 52 SEG16 PGIAIN 10 51 SEG17 PGIAIN 11 50 SEG18 PGIAOUT 12 49 SEG19 OP1IN 13 48 SEG20 OP1IN 14 47 SEG2...

Страница 10: ...clock input output Built in pull up resisters P5 1 SI I O Port 5 1 bi direction pin and SIO s data input Built in pull up resisters P5 2 SO I O Port 5 2 bi direction pin and SIO s data output Built in...

Страница 11: ...on 1 0 PIN CIRCUIT DIAGRAMS Figure 1 2 Pin Circuit Diagram Port0 structure PUR P0UR Pin Int bus PUR P2UR Pin Port2 structure Int bus LCD wave form P2SEG PUR P2UR Pin Port2 structure Int bus LCD wave f...

Страница 12: ...bit TC0 as 5 bit counter TC0_Count 4 bit TC0 as 4 bit counter 8 bit TC1 as 8 bit counter 6 bit TC1 as 6 bit counter 5 bit TC1 as 5 bit counter TC1_Count 4 bit TC1 as 4 bit counter Enable Enable Noise...

Страница 13: ...ector addresses 5 words reserved area 8K words general purpose area All of the program memory is partitioned into two coding areas located from 0000H to 0008H and from 0009H to 0FFEH Former area is as...

Страница 14: ...f program INTERRUPT VECTOR ADDRESS 0008H A 1 word vector address area is used to execute interrupt request If any interrupt service is executed the program counter PC value is stored in stack buffer a...

Страница 15: ...0XCH A ACCBUF B0XCH doesn t change C Z flag PUSH Push 80H 87H system registers POP Pop 80H 87H system registers B0XCH A ACCBUF RETI End of interrupt service routine ENDP End of program Remark it is ea...

Страница 16: ...0BSET FC clear C flag ADD DATA1 A add A to Data1 MOV A R ADC DATA2 A add R to Data2 JMP END_CHECK check if the YZ address the end of code AAA INCMS Z Z Z 1 JMP B if Z 00H calculate to next address JMP...

Страница 17: ...ata of ROM stores in ACC and high byte data stores in R register Example To look up the ROM data located TABLE1 B0MOV Y TABLE1 M To set look up table1 s middle address B0MOV Z TABLE1 L To set look up...

Страница 18: ...example for detailed information Example Increase Y and Z register by B0ADD ADD instruction B0MOV Y TABLE1 M To set look up table s middle address B0MOV Z TABLE1 L To set look up table s low address...

Страница 19: ...MP A3POINT ACC 3 jump to A3POINT In following example the jump table starts at 0x00FD When executing B0ADD PCL A ACC 0 or 1 the jump table points to the right address If the ACC is larger then 1 will...

Страница 20: ...d MACRO3 H B0MOV A BUF0 BUF0 is from 0 to 4 JMP_A 5 The number of the jump table listing is five JMP A0POINT If ACC 0 jump to A0POINT JMP A1POINT ACC 1 jump to A1POINT JMP A2POINT ACC 2 jump to A2POIN...

Страница 21: ...ster The bank 15 is LCD RAM area designed for storing LCD display data RAM location 000h General purpose area 000h 07Fh of Bank 0 To store general purpose data 128 bytes 07Fh 080h System register 080h...

Страница 22: ...ruction can access the RAM of bank 0 in any RBANK situation Example Access bank 0 data when RBANK points to bank 1 BANK 1 B0BSET RBNKS0 Get into RAM bank 1 B0MOV A BUF0 Read BUF0 data BUF0 is in RAM b...

Страница 23: ...to read write data through HL The Lower 4 bit of H register is pointed to RAM bank number and L register is pointed to RAM address number respectively The higher 4 bit data of H register is truncated...

Страница 24: ...e YZ is data point_1 index buffer located at address E7H in RAM bank 0 It employs Y and Z registers to addressing RAM location in order to read write data through YZ The Lower 4 bit of Y register is p...

Страница 25: ...2 Bit 1 Bit 0 X XBIT7 XBIT6 XBIT5 XBIT4 XBIT3 XBIT2 XBIT1 XBIT0 R W R W R W R W R W R W R W R W Note Please consult the LOOK UP TABLE DESCRIPTION about X register look up table application R REGISTERS...

Страница 26: ...e enter sleep mode CPUM 1 0 01 1 1 External reset or LVD active Note Watchdog timer is still running even Watchdog code option is disabled User can disable watchdog code option then treat NT0 NPD as a...

Страница 27: ...Write ACC data from BUF data memory MOV A BUF PUSH and POP instructions don t store ACC value as any interrupt service executed ACC must be stored in another data memory defined by users Once interru...

Страница 28: ...ogram counter PC data Figure 3 3 Stack Save and Stack Restore Operation STACK BUFFER STK7H STK6H STK5H STK4H STK3H STK2H STK1H STK0H STK7L STK6L STK5L STK4L STK3L STK2L STK1L STK0L STKP 0 STKP 1 STKP...

Страница 29: ...service routine Stack operation is a LIFO type Last in and first out The stack pointer STKP and stack buffer STKNH and STKNL are located in the bank 0 STKP stack pointer initial value 0xxx 1111 0DFH...

Страница 30: ...STK4H STK4L 5 1 0 1 0 STK5H STK5L 6 1 0 0 1 STK6H STK6L 7 1 0 0 0 STK7H STK7L 8 Stack Overflow Table 3 1 STKP STKNH and STKNL relative of Stack Save Operation There is a Stack Restore operation corres...

Страница 31: ...ram execution Besides it can be replaced with specific address by executing CALL or JMP instruction When JMP or CALL instruction is executed the destination address will be inserted to bit 0 bit 11 PC...

Страница 32: ...Zero flag 0 JMP C1STEP Else jump to C1STEP C1STEP NOP If the ACC is equal to the immediate data or memory then PC will add 2 steps to skip next instruction CMPRS A 12H Skip next instruction if ACC 12H...

Страница 33: ...on If carry signal occurs after execution of ADD PCL A the carry signal will not affect PCH register Example If PC 0323H PCH 03H PCL 23H PC 0323H MOV A 28H B0MOV PCL A Jump to address 0328H PC 0328H M...

Страница 34: ...OV 12H A Directly addressing mode B0MOV A 12H To get a content of location 12H of bank 0 and save in ACC INDIRECTLY ADDRESSING MODE The indirectly addressing mode is to set up an address in data point...

Страница 35: ...AM bank 1 this area memory can be read written by these two access methods Example 1 To use directly addressing mode Through RBANK register B0MOV RBANK 01H To set RAM bank 1 MOV A 12H To move content...

Страница 36: ...register arrangement of SN8P1829 Description L H Working HL addressing register R Working register and ROM look up data buffer Y Z Working YZ and ROM addressing register OPTION RTC and RCLK options PF...

Страница 37: ...SIOR5 SIOR4 SIOR3 SIOR2 SIOR1 SIOR0 W SIOR 0B6H SIOB7 SIOB6 SIOB5 SIOB4 SIOB3 SIOB2 SIOB1 SIOB0 R W SIOB 0BFH PEDGEN P00G1 P00G0 R W PEDGE 0C0H P13W P12W P11W P10W W P1W 0C1H P13M P12M P11M P10M R W P...

Страница 38: ...3PC3 S3PC2 S3PC1 S3PC0 R W STK3L 0F9H S3PC12 S3PC11 S3PC10 S3PC9 S3PC8 R W STK3H 0FAH S2PC7 S2PC6 S2PC5 S2PC4 S2PC3 S2PC2 S2PC1 S2PC0 R W STK2L 0FBH S2PC12 S2PC11 S2PC10 S2PC9 S2PC8 R W STK2H 0FCH S1P...

Страница 39: ...tector LVD The external reset is a simple RC circuit connecting to the reset pin The low voltage detector LVD is built in internal circuit When one of the reset devices occurs the system will reset an...

Страница 40: ...external reset circuit to control system operation It is necessary that the VDD must be stable External Reset VDD Internal Reset Signal External Reset Detect Level End of External Reset System Reset F...

Страница 41: ...e the error Figure 6 4 External Reset Circuit with Diode LOW VOLTAGE DETECTOR LVD DESCRIPTION The LVD is a low voltage detector It detects VDD level and reset the system as the VDD lower than the desi...

Страница 42: ...les Basic timer T0 Timer counter 0 TC0 Timer counter 1 TC1 Watchdog timer Serial I O interface SIO AD converter PWM output PWM0OUT PWM1OUT Buzzer output TC0OUT TC1OUT CLOCK BLOCK DIAGRAM fl CPUM0 LXOS...

Страница 43: ...or If STPHX 1 the external low speed RC oscillator is still running CLKMD System high Low speed mode select bit 0 normal dual mode 1 slow mode CPUM1 CPUM0 CPU operating mode control bit 00 normal 01 s...

Страница 44: ...tor types and frequencies High speed crystal needs more current but the low one doesn t For crystals there are three steps to select If the oscillator is RC type to select RC and the system will divid...

Страница 45: ...iver SONiX TECHNOLOGY CO LTD Page 45 Version 1 0 SYSTEM OSCILLATOR CIRCUITS MCU XIN VDD XOUT VSS CRYSTAL 20PF 20PF Figure 7 2 Crystal Ceramic Oscillator MCU XIN VDD VSS XOUT C R Figure 7 3 RC Oscillat...

Страница 46: ...er terminal Note2 The external clock input mode can select RC type oscillator or crystal type oscillator of the code option and input the external clock into XIN pin Note3 In RC type oscillator code o...

Страница 47: ...rm whose frequency is FCPU The other measures the external RC frequency by instruction cycle FCPU The external RC frequency is the FCPU multiplied by 4 We can get the FOSC frequency of external RC fro...

Страница 48: ...get into normal mode power down mode and green mode To set STPHX 1 to stop the external high speed oscillator and then the system consumes less power GREEN MODE The green mode is a less power consumpt...

Страница 49: ...Reset Table 7 1 Oscillator Operating Mode Description Note In the green mode T0 trigger signals can switch CPU return to the last mode If the system was into green mode from normal mode the system ret...

Страница 50: ...rn on the external high speed oscillator B0MOV Z 27 If VDD 5V internal RC 32KHz typical will delay DECMS Z 0 125ms X 81 10 125ms for external clock stable JMP B B0BCLR FCLKMD Change the system back to...

Страница 51: ...aits for 2048 external high speed oscillator clocks as the wakeup time to stable the oscillator circuit After the wakeup time the system goes into the normal mode The value of the wakeup time is as th...

Страница 52: ...Bit7 PEDGEN Interrupt and wakeup trigger edge control bit 0 Disable edge trigger function Port 0 Low level wakeup trigger and falling edge interrupt trigger Port 1 Low level wakeup trigger 1 Enable e...

Страница 53: ...modes OSCM initial value 0000 000x 0CAH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OSCM WTCKS WDRST WDRATE CPUM1 CPUM0 CLKMD STPHX R W R W R W R W R W R W R W Bit1 STPHX External high speed oscil...

Страница 54: ...age 54 Version 1 0 Note The watchdog timer can be enabled or disabled by the code option Example An operation of watchdog timer is as following To clear the watchdog timer s counter in the top of the...

Страница 55: ...0RATE2 T0RATE1 T0RATE0 TC1X8 TC0X8 TC0GN T0TB R W R W R W R W R W R W R W R W Bit7 T0ENB T0 timer control bit 0 disable 1 enable Bit 6 4 T0RATE2 T0RATE0 The T0 timer s clock source selects bits T0RATE...

Страница 56: ...C0 timer counter is as following 8 bit programmable timer Generates interrupts at specific time intervals based on the selected clock frequency Arbitrary frequency output Buzzer output Outputs selecta...

Страница 57: ...R W Bit7 TC0ENB TC0 counter BZ0 PWM0OUT enable bit 0 disable 1 enable Bit 6 4 TC0RATE 2 0 TC0 clock source selection bits TC0X8 is 2nd bit of T0M register TC0 Clock Source TC0RATE 2 0 TC0X8 0 TC0X8 1...

Страница 58: ...requency and TC0_Counter set TC0 became 8 bit 6 bit 5 bit or 4 bit counter The equation of TC0C initial value is as following TC0C initial value N TC0 interrupt interval time input clock Which N is de...

Страница 59: ...16 1 14 ms 17 9us 125 ms 1 95 ms 101 FCPU 8 0 57 ms 8 94us 62 5 ms 0 98 ms 110 FCPU 4 0 285 ms 4 47us 31 25 ms 0 49 ms 111 FCPU 2 0 143 ms 2 23us 15 63 ms 0 24 ms TC0_Counter 5 bit TC0X8 0 High speed...

Страница 60: ...ms 101 FOSC 4 71 5 us 1 117us 7 81ms 0 122 ms 110 FOSC 2 35 75 us 0 587us 3 905 ms 0 061 ms 111 FOSC 17 875 us 0 279us 1 953 ms 0 03 ms TC0_Counter 5 bit TC0X8 1 High speed mode FOSC 3 58MHz Low speed...

Страница 61: ...TC0C when the TC0C overflow ALOAD0 1 Store the duty value of PWM0OUT function TC0R initial value xxxx xxxx 0CDH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TC0R TC0R7 TC0R6 TC0R5 TC0R4 TC0R3 TC0R...

Страница 62: ...To select TC0 Fcpu 2 as clock source B0BCLR FTC0IEN To disable TC0 interrupt service B0BCLR FTC0ENB To disable TC0 timer MOV A 20H B0MOV TC0M A To set TC0 clock FCPU 64 MOV A 74H To set TC0C initial...

Страница 63: ...vice routine JMP EXIT_INT End of TC0 interrupt service routine and exit interrupt vector EXIT_INT B0MOV A PFLAGBUF B0MOV PFLAG A B0XCH A ACCBUF Restore ACC value RETI Exit interrupt vector Example TC0...

Страница 64: ...to output multi frequency Figure 8 2 The TC0OUT Pulse Frequency Example Setup TC0OUT output from TC0 to TC0OUT P5 4 The external high speed clock is 4MHz The TC0OUT frequency is 1KHz Because the TC0OU...

Страница 65: ...245 5 6818 22 0 2671 78 0 3511 134 0 5123 190 0 9470 246 6 2500 23 0 2682 79 0 3531 135 0 5165 191 0 9615 247 6 9444 24 0 2694 80 0 3551 136 0 5208 192 0 9766 248 7 8125 25 0 2706 81 0 3571 137 0 5252...

Страница 66: ...22 1 0684 78 1 4045 134 2 0492 190 3 7879 246 25 0000 23 1 0730 79 1 4124 135 2 0661 191 3 8462 247 27 7778 24 1 0776 80 1 4205 136 2 0833 192 3 9063 248 31 2500 25 1 0823 81 1 4286 137 2 1008 193 3 9...

Страница 67: ...Block Diagram The main purposes of the TC1 timer is as following 8 bit programmable timer Generates interrupts at specific time intervals based on the selected clock frequency Arbitrary frequency out...

Страница 68: ...counter BZ1 PWM1OUT enable bit 0 disable 1 enable Bit 6 4 TC1RATE 2 0 TC1 clock source selection bits TC1X8 is bit 3 of T0M register TC1 Clock Source TC1RATE 2 0 TC1X8 0 TC1X8 1 000 FCPU 256 FOSC 1024...

Страница 69: ...from FCPU and TC1_Counter set TC1 became 8 bit 6 bit 5 bit or 4 bit counter The equation of TC1C initial value is as following TC1C initial value N TC1 interrupt interval time input clock Which N is d...

Страница 70: ...16 1 14 ms 17 9us 125 ms 1 95 ms 101 FCPU 8 0 57 ms 8 94us 62 5 ms 0 98 ms 110 FCPU 4 0 285 ms 4 47us 31 25 ms 0 49 ms 111 FCPU 2 0 143 ms 2 23us 15 63 ms 0 24 ms TC1_Counter 5 bit TC1X8 0 High speed...

Страница 71: ...ms 101 FOSC 4 71 5 us 1 117us 7 81ms 0 122 ms 110 FOSC 2 35 75 us 0 587us 3 905 ms 0 061 ms 111 FOSC 17 875 us 0 279us 1 953 ms 0 03 ms TC1_Counter 5 bit TC1X8 1 High speed mode FOSC 3 58MHz Low speed...

Страница 72: ...TC1C when the TC1C overflow ALOAD1 1 Store the duty value of PWM1OUT function TC1R initial value xxxx xxxx 0DEH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TC1R TC1R7 TC1R6 TC1R5 TC1R4 TC1R3 TC1R...

Страница 73: ...B0BCLR FTC1X8 B0BCLR FTC1IEN To disable TC1 interrupt service B0BCLR FTC1ENB To disable TC1 timer MOV A 20H B0MOV TC1M A To set TC1 clock Fcpu 64 MOV A 74H To set TC1C initial value 74H B0MOV TC1C A T...

Страница 74: ...vice routine JMP EXIT_INT End of TC1 interrupt service routine and exit interrupt vector EXIT_INT B0MOV A PFLAGBUF B0MOV PFLAG A B0XCH A ACCBUF Restore ACC value RETI Exit interrupt vector Example TC1...

Страница 75: ...s buzzer output to output multi frequency Figure 8 4 TC1OUT Pulse Frequency Example Setup TC1OUT output from TC1 to TC1OUT P5 3 The external high speed clock is 4MHz The TC1OUT frequency is 1KHz Becau...

Страница 76: ...on of TC0_Counter TC1_Counter will cause different PWM Duty so user can generate different PWM output by selection different TC0_Counter TC1_Counter PWM output can be held at low level by continuously...

Страница 77: ...00 0001 1 256 1 64 1 32 1 16 0000 0010 2 256 2 64 2 32 2 16 0000 1110 14 256 14 64 14 32 14 16 0000 1111 15 256 15 64 15 32 15 16 0001 0000 16 256 16 64 16 32 N A N A 0001 1110 30 256 30 64 30 32 N A...

Страница 78: ...54 255 0 1 128 254 255 TC0 TC1 Clock TC0R TC1R 00H Low High Low Low High TC0R TC1R 01H TC0R TC1R 80H TC0R TC1R FFH Low High Low High 0 1 128 254 255 0 1 128 254 255 0 1 128 254 255 0 1 128 254 255 0 T...

Страница 79: ...ET FTC0ENB Enable TC0 timer Note1 The TC0R and TC1R are write only registers Don t process them using INCMS DECMS instructions Note2 Set TC0C at initial is to make first duty cycle correct After TC0 i...

Страница 80: ...ter will clear to 0 for stopping other interrupt request When interrupt service exits the GIE bit will set to 1 to accept the next interrupts request All of the interrupt request signals are stored in...

Страница 81: ...dication flags Each one of these interrupt request occurs the bit of the INTRQ register would be set 1 The INTRQ value needs to be clear by programming after detecting the flag In the interrupt vector...

Страница 82: ...pts start work after the GIE 1 It is necessary for interrupt service request One of the interrupt requests occurs and the program counter PC points to the interrupt vector ORG 8 and the stack add 1 le...

Страница 83: ...00 reserved 01 falling edge 10 rising edge 11 rising falling bi direction Example INT0 interrupt request setup B0BSET FP00IEN Enable INT0 interrupt service B0BCLR FP00IRQ Clear INT0 interrupt request...

Страница 84: ...make the P01IRQ to be 1 but the system will not enter interrupt vector Users need to care for the operation under multi interrupt situation Example INT1 interrupt request setup B0BSET FP01IEN Enable...

Страница 85: ...ion Example T0 interrupt request setup B0BCLR FT0IEN Disable T0 interrupt service B0BCLR FT0ENB Disable T0 timer MOV A 20H B0MOV T0M A Set T0 clock FCPU 64 MOV A 74H Set T0C initial value 74H B0MOV T0...

Страница 86: ...le TC0 interrupt request setup B0BCLR FTC0IEN Disable TC0 interrupt service B0BCLR FTC0ENB Disable TC0 timer MOV A 20H B0MOV TC0M A Set TC0 clock FCPU 64 MOV A 74H Set TC0C initial value 74H B0MOV TC0...

Страница 87: ...le TC1 interrupt request setup B0BCLR FTC1IEN Disable TC1 interrupt service B0BCLR FT C1ENB Disable TC1 timer MOV A 20H B0MOV TC1M A Set TC1 clock FCPU 64 MOV A 74H Set TC1C initial value 74H B0MOV TC...

Страница 88: ...to be 1 but the system will not enter interrupt vector Users need to care for the operation under multi interrupt situation Example SIO interrupt request setup B0BSET FSIOIEN Enable SIO interrupt ser...

Страница 89: ...red by the events without interrupt enable Just only any the event occurs and the IRQ will be logic 1 The IRQ and its trigger event relationship is as the below table Interrupt Name Trigger Event Desc...

Страница 90: ...terrupt service routine INTT0CHK Check T0 interrupt request B0BTS1 FT0IEN Check T0IEN JMP INTTC0CHK Jump check to next interrupt B0BTS0 FT0IRQ Check T0IRQ JMP INTT0 Jump to T0 interrupt service routin...

Страница 91: ...to reload function The 3 bit I O counter can monitor the operation of SIO and announce an interrupt request after transmitting receiving 8 bit data After transferring 8 bit data this circuit will be d...

Страница 92: ...ta transfer When both processors must work in the same clock edge both controllers would send and receive data at the same time Figure 10 2 SIO Data Transfer Diagram MSB LSB MSB LSB PROCESS 1 PROCESS...

Страница 93: ...bit 0 End of transmit 1 Progressing SRATE 1 0 SIO transmit rate select bit 00 FCPU 01 FCPU 32 10 FCPU 16 11 FCPU 8 Note These 2 bits are workless when SCKMD 1 SIG Start SIO receiver function automati...

Страница 94: ...ENB 0 SIO Function Disable P5 0 P5 1 P5 2 Port5 2 0 I O mode are fully controlled by P5M when SIO function Disable SIOB DATA BUFFER SIOB initial value 0000 0000 0B6H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit...

Страница 95: ...ng edge MOV A TXDATA Load transmitted data into SIOB register B0MOV SIOB A MOV A 0FFH Set SIO clock with auto reload function B0MOV SIOR A MOV A 10000011B Setup SIOM and enable SIO function Rising edg...

Страница 96: ...et SIO clock with auto reload function B0MOV SIOR A MOV A 10000001B Setup SIOM and enable SIO function Falling edge B0MOV SIOM A B0BSET FSTART Start transfer and receiving SIO data CHK_END B0BTS0 FSTA...

Страница 97: ...reload function B0MOV SIOR A MOV A 10000010B Setup SIOM and enable SIO function Rising edge B0MOV SIOM A B0BSET FSTART Start receiving SIO data CHK_END B0BTS0 FSTART Wait the end of SIO operation JMP...

Страница 98: ...reload function B0MOV SIOR A MOV A 10000000B Setup SIOM and enable SIO function Falling edge B0MOV SIOM A B0BSET FSTART Start receiving SIO data CHK_END B0BTS0 FSTART Wait the end of SIO operation JMP...

Страница 99: ...ulator 128 dots LCD driver SONiX TECHNOLOGY CO LTD Page 99 Version 1 0 SIO SLAVE OPERATING DESCRIPTION Under slave receiver situation the SCK has four phases as following SCK4 SCK3 SCK2 SCK1 Figure 10...

Страница 100: ...enable SIO function Rising edge B0MOV SIOM A B0BSET FSTART Start transfer and receiving SIO data CHK_END B0BTS0 FSTART Wait the end of SIO operation JMP CHK_END B0MOV A SIOB Save SIOB data into RXDAT...

Страница 101: ...enable SIO function Falling edge B0MOV SIOM A B0BSET FSTART Start transfer and receiving SIO data CHK_END B0BTS0 FSTART Wait the end of SIO operation JMP CHK_END B0MOV A SIOB Save SIOB data into RXDA...

Страница 102: ...ction Rising edge B0MOV SIOM A B0BSET FSTART Start receiving SIO data CHK_END B0BTS0 FSTART Wait the end of SIO operation JMP CHK_END B0MOV A SIOB Save SIOB data into RXDATA buffer MOV RXDATA A LSB DI...

Страница 103: ...ction Falling edge B0MOV SIOM A B0BSET FSTART Start receiving SIO data CHK_END B0BTS0 FSTART Wait the end of SIO operation JMP CHK_END B0MOV A SIOB Save SIOB data into RXDATA buffer MOV RXDATA A DI5 D...

Страница 104: ...terrupt request occurring There is an example for the application as following Example SIO interrupt demo routine Main MOV A 10000100B Setup SIOM and enable SIO function Falling edge B0MOV SIOM A B0BS...

Страница 105: ...orts P0 P2 two I O ports P1 P5 The direction of I O port is selected by PNM register Figure 11 1 The I O Port Block Diagram Note All of the latch output circuits are push pull structures Port0 structu...

Страница 106: ...P2 7 I LCD segment General purpose input output function P5 0 I O SIO clock pin I O General purpose input output function P5 1 I SIO data input pin P5M 1 must be set 0 I O General purpose input output...

Страница 107: ...mode P5M initial value 0000 0000 0C5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P5M 0 0 0 P54M P53M P52M P51M P50M R W R W R W R W R W P50M P54M P5 0 P5 4 I O direction control bit 0 input mode...

Страница 108: ...4 SEG31 LCD driver pins The port2 must work without LCD To set the bit P2SEG 1 the port 2 Input function will be enabled Input data from port 2 is by P2 data register Example Enable PORT 2 Input funct...

Страница 109: ...2 Bit 1 Bit 0 P2 P27 P26 P25 P24 P23 P22 P21 P20 R R R R R R R R P5 initial value xxx0 0000 0D5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P5 P54 P53 P52 P51 P50 R W R W R W R W R W Example Read...

Страница 110: ...pins eight segment pins are shared with Port 2 and P2 SEG functions can be selected by programming LCDM1 register LCDM1 REGISTER LCDM1 register initial value xx0x 00x1 0CBH Bit 7 Bit 6 Bit 5 Bit 4 Bit...

Страница 111: ...nel users can add external resistor to bias pin V1 V2 V3 to adjust bias voltage and LCD drive current Too much or less current makes the LCD to bring remnant images In normal condition the external bi...

Страница 112: ...Version 1 0 LCD TIMING F frame External Low clock 384 Ex External low clock is 32768Hz The F frame is 32768Hz 384 85 3Hz Note The clock source of LCD driver is external low clock COM0 COM1 COM2 COM3 S...

Страница 113: ...PGIA Charge pump Regulator 128 dots LCD driver SONiX TECHNOLOGY CO LTD Page 113 Version 1 0 COM0 COM1 COM2 COM3 SEG0 1 frame 1 frame LCD Clock VLCD V3 V1 LCD OFF OFF ON ON V2 VLCD V3 V1 V2 Figure 12...

Страница 114: ...2 01H 3 SEG 2 02H 0 02H 1 02H 2 02H 3 SEG 3 03H 0 03H 1 03H 2 03H 3 SEG 14 0EH 0 0EH 1 0EH 2 0EH 3 SEG 15 0FH 0 0FH 1 0FH 2 0FH 3 SEG 16 10H 0 10H 1 10H 2 10H 3 SEG 17 11H 0 11H 1 11H 2 11H 3 SEG 29 1...

Страница 115: ...C circuit can select 8 bit or 12 bit resolution operation by programming ADLEN bit in ADR register ADC AIN0 AIN1 AIN2 VDD AGND 00 01 10 11 11 CHS 1 0 AVREFH AVREFL DATA BUS 8 12 Charge Pump Regulator...

Страница 116: ...0 Progressing 1 End of converting and reset ADS bit Bit6 ADS ADC starts bit 0 stop 1 starting Bit7 ADENB ADC control bit 0 disable 1 enable ADR REGISTERS ADR initial value x00x 0000 0B3H Bit 7 Bit 6...

Страница 117: ...hen power on The AIN s input voltage vs ADB s output data AIN n ADB11 ADB10 ADB9 ADB8 ADB7 ADB6 ADB5 ADB4 ADB3 ADB2 ADB1 ADB0 0 4096 AVREFH 0 0 0 0 0 0 0 0 0 0 0 0 1 4096 AVREFH 0 0 0 0 0 0 0 0 0 0 0...

Страница 118: ...us 1 0 Fhosc 1 3 58MHz 4 16 17 9 us 1 12 bit 1 1 Fhosc 2 1 3 58MHz 2 4 16 35 8 us Example To set AIN0 AIN1 for ADC input and executing 12 bit ADC ADC0 MOV A 60H B0MOV ADR A To set 12 bit ADC and ADC c...

Страница 119: ...ed programmable gain instrumentation amplifier PGIA with selectable gains stage one of16x 32x 64x 128x and gains stage two of 1 3x 2 5x BLOCK DIAGRAM Figure 14 1 illustrates a block diagram of the Cha...

Страница 120: ...for output voltage stabilization after set CPRENB to high CPM Charge Pump Mode Register 095H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CPM CPSTS CPAUTO CPON CPRENB R R W R W R W CPRENB Charge Pu...

Страница 121: ...OFF depended on VDD voltage Auto Mode Description CPRENB CPON CPAUTO VDD Charge Pump Status CPSTS Regulator Status AVDDR Output PGIA ADC OPA Power Supply 4 1V OFF 0 ON 3 8V 3 8V 1 0 1 4 1V ON 1 ON 3 8...

Страница 122: ...e following table for CPCKS 7 0 register value setting in different Fosc frequency Charge Pump Clock Fosc 256 CPCKS 7 0 2 CPCKS 7 0 FOSC CP Working Clock 236 4M 4M 20 2 100K 216 8M 8M 40 2 100K 206 10...

Страница 123: ...PGIA Gain1 selection control bit P2GS 3 0 PGIA Gain2 selection control bit P1GS 1 0 00 01 10 11 P2GS 3 0 Gain 16 32 64 128 0000 1 32558 21 2093 42 4186 84 8372 169 674 0001 1 38095 22 0952 44 1905 88...

Страница 124: ...10M 100 8 12 5K 136 12M 12M 120 8 12 5K 56 20M 20M 200 8 12 5K Note In general application PGIA working clock is 12 5K Hz Example PGIA setting Fosc 4M X tal CPREG_Init Enable Charge Pump Regulator bef...

Страница 125: ...ional amplifiers OPA for low pass filer or constant current source circuit OPM OPA Mode Register 09BH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OPM OP2ENB OP1IENB R W R W OP1ENB Operation amplif...

Страница 126: ...K Y2 4M AGND AVDDR AVREFL AIN0 AIN1 AVREFH VSS 20P 20P 20P 20P LXIN LXOUT XIN XOUT AVDDCP VDD 10uF C C VSS VDD VBAT 10uF RST VDD3A VLCD V1 V2 V3 SEG31 SEG32 SEG27 SEG22 SEG24 VDD1 SEG23 SEG8 SEG9 SEG7...

Страница 127: ...1 L AND M A M A and M 1 O AND A I A A and I 1 G OR A M A A or M 1 I OR M A M A or M 1 C OR A I A A or I 1 XOR A M A A xor M 1 XOR M A M A xor M 1 XOR A I A A xor I 1 SWAP M A b3 b0 b7 b4 M b7 b4 b3 b0...

Страница 128: ...DD V ViL3 Reset pin Xin in RC mode VSS 0 2VDD V Input Low Voltage ViL4 Xin in X tal mode VSS 0 3VDD V ViH1 All input pins except those specified below 0 7VDD VDD V ViH2 Input with Schmitt trigger buff...

Страница 129: ...ode AVDDR 3 8V 300 A Power down current IPDN Stop mode AVDDR 3 8V 0 1 A Input offset voltage of 1 st stage Vos1 5 uV Input offset voltage of 2 nd stage Vos2 2 mV GAIN of 1st stage Av1 16 128 GAIN of 2...

Страница 130: ...SN8P1829 8 Bit MCU build in 12 bit ADC PGIA Charge pump Regulator 128 dots LCD driver SONiX TECHNOLOGY CO LTD Page 130 Version 1 0 1 1 18 8 8 PACKAGE INFORMATION LQFP80...

Страница 131: ...personal injury or death may occur Should Buyer purchase or use SONIX products for any such unintended or unauthorized application Buyer shall indemnify and hold SONIX and its officers employees subs...

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