High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
259
Revision 1.4 (08-19-08)
DATASHEET
14.2.9
Miscellaneous
This section details the remainder of the System CSR’s. These registers allow for monitoring and
configuration of various LAN9312 functions such as the Chip ID/revision, byte order testing, power
management, hardware configuration, general purpose timer, and free running counter.
14.2.9.1
Chip ID and Revision (ID_REV)
This read-only register contains the ID and Revision fields for the LAN9312.
Note 14.46
Default value is dependent on device revision.
Offset:
050h
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31:16
Chip ID
This field indicates the chip ID.
RO
9312h
15:0
Chip Revision
This field indicates the design revision.
RO