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36 PMCspan PMC Carrier Module Installation and Use (6806800A59C)
Programming Model
Configuration Transactions
Table 4-2 PLX PCI6150 PCI Configuration Register Address Mapping
PCI
Configuration
Register
Address
31 24 23 16 15 8 7 0
PC
Writable
Serial
EEPROM
Writable
10h-17h Reserved No No
18h
Secondary
Latency
Subordinate
Bus Number Secondary
Bus Number Primary Bus
Number
Yes No
1Ch Secondary Status I/O Limit I/O Base Yes No
20h Memory Limit Memory Base Yes No
24h Prefetchable Memory Limit Prefetchable Memory Base Yes No
28h Prefetchable Memory Base Upper 32 Bits Yes No
2Ch Prefetchable Memory Limit Upper 32 Bits Yes No
30h I/O Limit Upper 16 Bits I/O Base Upper 16 Bits Yes No
34h
Reserved
New
Capability
Pointer (DCh
if Power
Management
Support;
otherwise,
No No
38h Reserved No No
3Ch Bridge Control Interrupt Pin Reserved Yes No
40h Arbiter Control
Diagnostic
Control
Chip Control Yes No
44h Miscellaneous Options
Timeout
Control
Primary
Flow-
Yes Yes
48h
Secondary
Incremental
Prefetch Primary
Incremental
Prefetch
Secondary
Prefectch
LineCount Primary
Prefetch Line
Count
Yes Yes
4Ch Reserved
Secondary
Flow-through
Control
Secondary
Maximum
Prefectch
Count Primary
Maximum
Prefetch
Count
Yes Yes
50h Reserved Test Internal Arbiter Control Yes No