SMART PMCspan, Руководство пользователя

Страница: 33 / 64

PMC Performance
PMCspan PMC Carrier Module Installation and Use (6806800A59C) 33
The following table shows the access timings for various types of transfers initiated by a
60X system bus master to a PMCspan module.
The next table shows the ECC memory access latency for PMCspan-initiated cycles.
Notes
:
1. The latency assumes two system clocks for 60x system bus arbitration.
2. The latency is based on 60ns, fast-page DRAM timing. It is also assumed that L2 is
either disabled or missed.
3. Write timings assume write posting FIFO is initially empty.
Table 3-1 PowerPC 60x Bus to PMCspan PMC Access Timing
Access Type System Total
Clocks
1st Beat 2nd Beat 3rd Beat 4th Beat
4-Beat Read (32-bit PCI Target) 49 1 1 1 52
4-Beat Write (32-bit PCI Target) 4 1 1 1 7
1-Beat Read (aligned, 4 bytes or
less)
38 - - - 38
1-Beat Write 4 - - - 4
Notes:
Write cycles are posted by the Raven ASIC.
Assumes no pipeline. Pipelined cycles would improve these numbers.
T
arb
is assumed to be 4 system clocks (2 PCI clocks).
T
ac
is assumed to be 6 system clocks (3 PCI clocks): Medium DEVSEL# target, zero wait PCI timing.
Table 3-2 PMCspan PMC to ECC Memory Access Timing
Access Type PCI Clock Periods
Required for:
1st Beat 2nd Beat 3rd Beat nth Beat
32-bit Burst Reads 17 1 1 1
32-bit Burst Writes 3 1 1 1
1-Beat Read 17 - - -
1-Beat Write 3 - - -