2. Family Product Comparison
The following table is a comparison of the different parts in the product family showing the differences in the inputs, MultiSynths, outputs
and package type.
Table 2.1. Family Feature Comparison
Part Number
Number of Inputs
Number of
Fractional Dividers
Number of Outputs
Package Type
Si5391
4
5
12
64-pin QFN
2.1 Grade P (Precision) Restrictions and Requirements
Some applications like 56G PAM4 SERDES require even higher performance than is already provided by standard clock generators.
The Si5391P (Precision) grade internally calibrates out linearity errors to deliver the world's best jitter performance for output clocks
of 156.25, 312.5, and 625 MHz frequencies. The grade 'P' part XTAL frequency is fixed at 48 MHz and variation must be within ±100
ppm across temperature, load capacitance mismatch and aging. The P (Precision) grade part has various restrictions compared to the
highly flexible A grade device. These restrictions are required to guarantee the 100-fs integrated jitter specification in the 12kHz-20MHz
frequency band for 156.25MHz, 312.5MHz, and 625MHz output frequencies.
This section identifies most of the restrictions/rules required to achieve <100 fs jitter.
2.2 Si5391P Grade Frequency Plan Rules
In order to achieve <100 fs jitter on the 156.25/312.5/625 output clocks there are various restrictions/rules that must be met regarding
output clock placement, format, and separation. The following restrictions/rules and a few more are implemented in CBPro with
visual feedback so that it is simple to develop a plan that guarantees <100 fs jitter on the 156.25/312.5/625 MHz output clocks. A
156.25/312.5/625 MHz output will be labeled by CBPro as “Precision” when it will achieve less than 100 fs jitter.
2.2.1 Output Clock Domains
The Si5391P is only allowed to output a fixed set of frequencies. These frequencies are grouped into 3 clock domains.
•
Domain1:
125/156.25/312.5/625 MHz
•
Domain2:
25/50/100/125/200 MHz
•
Domain3:
322.265625/644.53125 MHz
125 MHz is a part of domain 1 and domain 2 because 125 MHz does not cause any crosstalk issues with the 156.25/312.5/625 MHz
outputs. Therefore, a 125 MHz output clock can be placed on any output location.
2.2.2 Output Clock Locations
The following are the clock locations to achieve < 100 fs jitter on the 156.25/312.5/625 MHz outputs. Additional rules that create gaps
between domain 1 clock locations and domain 2&3 locations are enforced by CBPro.
If Only Domain 1 Output Frequencies are Present:
Domain 1 frequencies can be placed in any output location and achieve <100 fs jitter on the 156.25/312.5/625 MHz outputs.
If Domain 1 as well as Domain 2 or 3 Output Frequencies are Present:
If only domain 1 and 2 output frequencies are present, then Table 2.2 applies. If domain 1, 2, and 3 output frequencies are present, then
Table 2.3 applies. If only domain 1 and 3 output frequencies are present, then Table 2.4 applies.
Si5391 Reference Manual • Family Product Comparison
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
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Rev. 0.5 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 11, 2022
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