SII LTP3445, Техническое описание

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2-18
2.5.6 Thermal Head Electrical Characteristics
Table 2-9 Thermal Head Electrical Characteristics (at Vdd=5V, 25
°
C)
Minimum
Item Symbol Conditions
MIN TYP MAX
Unit
Head resistance RH
145

178
Ω
Head drive voltage Vp
4.2

8.5
V
Logic block voltage Vdd
4.5 5.0 5.5
V
Waiting for activation
 
1.5
mA
fclk=4MHz , HDAT=Fixed
 
13
mA Logic block current Idd
fclk=4MHz , HDAT=HLHLHL--
 
26
mA
“
High
”
input voltage Vih
HCLK,HDAT,LATCH,DST
BCLK,BDAT,BCLR,CTRL
0.8
×
Vd
d

Vdd
V
“
Low
”
input voltage Vil
HCLK,HDAT,LATCH,DST
BCLK,BDAT,BCLR,CTRL
0

0.2
×
Vd
d
V
HCLK term

-

6.5
µ
A
HDAT,LATCH,BCLK,BDAT
 
10
µ
A
DST
 
455
µ
A
“
High
”
input current Iih
BCLR,CTRL
 
320
µ
A
HCLK term
 
-6.5
µ
A
HDAT,LATCH,BCLK,BDAT
 
-10
µ
A
DST
 
-6.5
µ
A
“
Low
”
input current Iil
BCLR,CTRL
 
-10
µ
A
“
High
”
output voltage Voh
4.45
 
V
“
Low
”
output voltage Vol
HDO, Vdd=4.5(V) at no load
 
0.05
V
“
High
”
output current Ioh HDO, Voh=Vdd-0.4(V)
-0.5
 
mA
“
Low
”
output current Iol HDO, Vol=0.4(V)
0.5
 
mA
HCLK,BCLK frequency fclk
 
4
MHz
HCLK pulse width t1 See the timing chart.
100
 
ns
CTRL setup time t2 See the timing chart.
20
 
ns
HDAT setup time t3 See the timing chart.
70
 
ns
HDAT hold time t4 See the timing chart.
20
 
ns
HDO output delay time t5 See the timing chart.
 
200
ns
LATCH setup time t6 See the timing chart.
100
 
ns
LATCH pulse width t7 See the timing chart.
120
 
ns
DST setup time 1 t8 See the timing chart.
100
 
ns
BCLK pulse width t9 See the timing chart.
100
 
ns
BDAT setup time t10 See the timing chart.
20
 
ns
BDAT hold time t11 See the timing chart.
20
 
ns
DST setup time 2 t12 See the timing chart.
20
 
ns
BCLR pulse width t13 See the timing chart.
20
 
ns