Siemens SIMATIC PCIe DIO4, Краткое руководство по эксплуатации

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Examples and register assignments
4.3 Registers
SIMATIC PCIe DIO4
30
Compact Operating Instructions, 11/2011, A5E03493449-01
If CxCR.CSEL = "0", the value of the register is compared with CxVR. If CxCR.CSEL = "1",
the value of the register is compared with CxCAPR. CxSR includes the comparison result:
CxSR.CE CxVR/CxCAPR is equal to CxCOMR.
CxSR.CG CxVR/CxCAPR is greater than CxCOMR.
CxSR.CS CxVR/CxCAPR is less than CxCOMR.
CxRELR: Counter x Reload Register (BASE + (x*0x100))
If the reload trigger CxTR3 is enabled, the register is written to the counter register CxVR.
Bit Access Name Default Description
35..0 RW REL 0 Reload value
CxCAPR: Counter x Capture Register (BASE + (x*0x100))
If the capture trigger CxTR4 is enabled, the current value of CxVR in saved in this register.
Bit Access Name Default Description
35..0 RW CAP 0 Capture value
PCIEIS: PCIe core Interrupt Status Register (BASE + 0x4040)
The register includes the interrupt status bit of the PCIe kernel.
Bit Access Name Default Description
31...8 RO Reserved
7 RO IA 0 Interrupt active: If this bit is set, the PCIe kernel signals
an interrupt to the system.
6...0 RO Reserved 0
PCIEIE: PCIe core Interrupt Enable Register (BASE + 0x4050)
The register includes the interrupt enable bit of the PCIe kernel. All bits with the exception of
bit 7 must be maintained and saved permanently.
Bit Access Name Default Description
31...8 RO Reserved
7 RW IE 0 Interrupt enable: If this bit is set, the PCIe kernel
forwards interrupts to the system. If this bit is not set, an
interrupt is not generated even if GCR.IEN is set.
6...0 RO Reserved 0