7SG1641 Ohmega 402 60 Diagrams
Voltage Memory
Title
Art No
Author
See diagram properties for revision history
Voltage Memory Support
2615S81251
Ken Nickerson
This diagram generates some control signals to latch/reset the zone1 and zone4 outputs when memory timeout occurs.
VMEM_ACTIVE
VMEM_TIMEOUT
&
&
VMT_FEEDBACK
VMT_FEEDBACK
VMEM_RECOVERED
VMEM_RECOVERED
IF_ALL_OFF
1
LatchResetDelayTimer
10 / 1
DPIF_IA
DPIF_IB
DPIF_IC
&
1
IF_ALL_ON
IF_ALL_OFF
Firstly, we generate a reset control from the distance fault current detectors
Next, we generate the latch control signals for use by the distance module output latches - first the latch enable
When a heavy three phase fault occurs, the fault voltage will collapse and the voltage memory will start timing out. After
approx 100ms, the memory output will clamp off and the memory timeout signal will go active. This applies an inhibit to zone
1 and (where fitted) zone 4. The latch operation is required to prevent dropoff of the trip relays too early because of removal of
of the comparator outputs. Reset occurs when memory recovers (voltage back) or the fault current is removed in all phases.
DPENABLEOUTPUTLATCH
DPRESETOUTPUTLATCH
Output to the distance module
Output to the distance module
Now the latch reset signal
©2011 Siemens Protection Devices Limited
Chapter 11 Page 7 of 18