12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0
250
500
750
1000
1250
Input voltage U [V]
L
o
a
d
re
s
ist
a
nc
e
R
[Ω
]
Figure 9: Permissible load resistances
8
CONNECTION
14
O P E R A T I N G I N S T R U C T I O N S | TMS/TMM22
8026576/1EF6/2021-12-13 | SICK
Subject to change without notice
