Sharp UP-5300, Руководство по обслуживанию

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Signal Name Pin No.
Signal Type
(Drive)
Selected By Signal Description
RFSH# J25 I/O PCIDV1
C2h[0] = 0 Refresh: As an output, this signal is used to inform FireStar to
refresh the local DRAM.
During normal operation, a low pulse is generated every 15
µ
s to
indicate to FireStar that the DRAM is to be refreshed if PCIDV1
64h[0] = 0.
During Suspend, if normal DRAM is used, the 32KHZ input to the
FireStar is routed out on this pin so that it may perform DRAM refresh.
An option to continuously drive this signal low during Suspend is also
provided. The internal pull-up on this pin is disengaged in Suspend.
SBHE# W25 I/O PCDIDV1
94h = 00h System Byte High Enable: When asserted, SBHE# indicates that a
byte is being transferred on the upper byte (SD[15:8]) of the data
bus. SBHE# is negated during refresh cycles. SBHE# is an output
when FireStar owns the ISA bus.
TC M23 I/O PCIDV1
C2h [2] = 0 Terminal Count
XD7 AA23 I/O
(8mA)
Cycle
Multiplexed
(See Note) XD Bus Line 7: ISA status signal.
IDE_DCS3# DCS3 Control for Primary IDE Channel
XD6 AA24 I/O
(8mA)
Cycle
Multiplexed
(See Note) XD Bus Line 6: ISA status signal.
IDE_DCS1# DCS1 Control for Primary IDE Channel
XD5 AA25 I/O
(8mA)
Cycle
Multiplexed
(See Note) XD Bus Line 5: ISA status signal.
IDE_DDACK# DMA Acknowledge for Primary IDE Channel
XD4 AA26 I/O
(8mA)
Cycle
Multiplexed
(See Note) XD Bus Line 4: ISA status signal.
IDE_DA2 Address Bit 2 for Primary IDE Channel
XD3 Y23 I/O
(8mA)
Cycle
Multiplexed
(See Note) XD Bus Line 3: ISA status signal.
IDE_DA1 Address Bit 1 for Primary IDE Channel
XD2 Y24 I/O
(8mA)
Cycle
Multiplexed
(See Note) XD Bus Line 2: ISA status signal.
IDE_DA0 Address Bit 0 for Primary IDE Channel
XD1 Y25 I/O
(8mA)
Cycle
Multiplexed
(See Note) XD Bus Line 1: ISA status signal.
IDE_DRD# Drive Read Control for Primary IDE Channel
XD0 Y26 I/O
(8mA)
Cycle
Multiplexed
(See Note) XD Bus Line 0: ISA status signal.
IDE_DWR# Drive Write Control for Primary IDE Channel
Note: XD[7:0] can be strapped to be dedicated IDE lines via the RTCAS:A20M# strap option and PCIDV1 75h[6] = 1
SA[23:20] V23:V26 I/O
(8mA)
System Address Bus Lines 23 through 20: The SA[23:0] signals
on FireStar provide the address for memory and I/O accesses on the
ISA bus. The address are outputs when FireStar owns the ISA bus
and are inputs when an external ISA master owns the ISA bus.
SA[19:18] U23:U24 I/O
(8mA)
System Address Bus Lines 19 and 18
SA[17:16] U25:U26 I/O
(8mA)
PCIDV1
91h-90h = 00h System Address Bus Lines 17 and 16
SA[15:0] I/O
(8mA)
System Address Bus Lines 15 through 0
External Real-Time Clock Interface
RTCAS N24 O
(4mA)
Real-Time Clock Address Strobe: This signal is connected to the
address strobe of the real-time clock.
RTCRD# N25 O
(4mA)
Real-Time Clock Read: This pin is used to drive the read signal of
the real-time clock.
RTCWR# N26 O
(4mA)
Real-Time Clock Write: This pin is used to drive the write signal of
the real-time clock.
Power Management Unit Interface
PPWR0# AC23 I/O BOFF# strap
option Peripheral Power Control Line 0#
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