Sharp UP-5300, Руководство по обслуживанию

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Signal Name Pin No.
Signal Type
(Drive)
Selected By Signal Description
NA# U4 O
(4mA)
Next Address: This signal is connected to the CPU’s NA# pin to
request pipelined addressing for local memory cycle. FireStar asserts
NA# for one clock when the system is ready to accept a new address
from the CPU, even if all data transfers for the current cycle have not
completed.
KEN# R2 O
(4mA)
Cache Enable: This pin is connected to the KEN# input of the CPU
and is used to determine whether the current cycle is cacheable.
EADS# T4 O
(4mA)
Cycle
Multiplexed External Address Strobe: This output indicates that a valid address
has been driven onto the CPU address bus by an external device.
This address will be used to perform an internal cache inquiry cycle
when the CPU samples EADS# active.
WB/WT# Writeback/Write-Through: Pin T4 is also used to control writeback
or write-though policy for the primary cache during CPU cycles.
HITM# R4 I Hit Modified: Indicates that the CPU has had a hit on modified line in
its internal cache during an inquire cycle. It is used to prepare for
writeback.
CACHE# T2 I Cacheability: This input is connected to the CACHE# pin of the
CPU. It goes active during a CPU initiated cycle to indicate when, an
internal cacheable read cycle or a burst writeback cycle, occurs.
AHOLD U3 O
(4mA)
Address Hold: This signal is used to tristate the CPU address bus
for internal cache snooping.
LOCK# U2 I CPU Bus Lock: The processor asserts LOCK# to indicate the
current bus cycle is locked. It is used to generate PLOCK# for the
PCI bus.
LOCK# has an internal pull-down resistor that is engaged when
HLDA is active.
BOFF# R5 O
(4mA)
Back-off: This pin is connected to the BOFF# input of the CPU.
Strap option
pin, refer to
Table 3-7
CPURST R1 O
(4mA)
(Always) CPU Reset: This signal generates a hard reset to the CPU whenever
the PWRGD input goes active.
RSMRST SYSCFG
ADh[5] = 1 Resume Reset: Generates a hard reset to the CPU on resuming
from Suspend mode.
Host Power Control
SMI# AE5 O
(4mA)
System Management Interrupt: This signal is used to request
System Management Mode (SMM) operation.
SMIACT# U1 I System Management Interrupt Active: The CPU asserts SMIACT#
in response to the SMI# signal to indicate that it is operating in
System Management Mode (SMM).
STPCLK# AE6 O
(4mA)
Stop Clock: This signal is connected to the STPCLK# input of the
CPU. It causes the CPU to get into the STPGENT# state.
L2 Cache Control
CDOE# P1 O
(4mA)
PCIDV1
80h = 00h Cache Output Enable: This signal is connected to the output
enables of the SRAMs of the L2 cache in both banks to enable data
read.
CACS# P3 O
(4mA)
See SYSCFG
16h[7,5] bit
descriptions on
page 266 Cache Chip Select: This pin is connected to the chip selects of the
SRAMs in the L2 cache to enable data read/write operations. If not
used, the CS# lines of the cache should be tied low.
DIRTY I/O
(4mA)
Tag Dirty Bit: This separate dirty bit allows the tag data to be 8 bits
wide instead of 7.
DIRTY is a 5.0V tolerant input, even when its power plane is
connected to 3.3V as long as the 5VREF pins of FireStar are
connected to +5.0V.
BWE# P4 O
(4mA)
Byte Write Enable: Write command to L2 cache indicating that only
bytes selected by BE[7:0]# will be written.
GWE# N1 O
(4mA)
SYSCFG
19h[7] = 0 Global Write Enable: Write command to L2 cache indicating that all
bytes will be written.
TAG0 E9 I/O
(4mA)
SYSCFG
11h[3] = 0 Tag RAM Data Bit 0: This input signal becomes an output whenever
TAGWE# is activated to write a new tag to the Tag RAM.
TAG1 D9 I/O
(4mA)
SYSCFG
00h[5] = 0
11h[3] = 0 Tag RAM Data Bit 1: This input signal becomes an output whenever
TAGWE# is activated to write a new tag to the Tag RAM.
TAG2 C9 I/O
(4mA)
SYSCFG
00h[5] = 0
11h[3] = 0 Tag RAM Data Bit 2: This input signal becomes an output whenever
TAGWE# is activated to write a new tag to the Tag RAM.
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