Sharp UP-3301, Руководство по обслуживанию

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UP-3301US CIRCUIT DESCRIPTION
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3-2. 0page area
The 0page area consists of three spaces:
1
the ROM mapped area,
2
internal and
3
external I/O areas.
The ROM mapped space have been devised for the following purposes:
1
Simplifying the procedure for booting the IPL program
2
Achieving high-speed accessing, and accessing by abbreviated
instructions.
Fig. 3
3-3. I/O areas
The addresses from 00FF80h to 00FFFFh are called the internal I/O
area.
The internal I/O area is a space where the control registers and built-in
ports inside the CPU are addressed.
The external I/O area is a space where the peripheral devices outside
the CPU or devices on an optional card are addressed.
Fig. 4
3-4. ROM space
Fig.5 shows the ROM space. The UP-3301 uses 2MB of NOR-type
flash memory instead of a conventional ROM, so that the ROS1 from
the MPCA8 is input into the chip enable of the flash memory.
Fig. 5
3-5. VRAM & RAM space
The VRAM is the display memory of the LCD.
Fig. 6
000000h
00FFFFh
00FF80h
00FE80h
Internal I/O area
External I/O area
ROM mapping area
I/O area
* The ROM area 200000h to
20FFFFh (ROS1 lower 64KB)
is mapped on the ROMmapping
area.
* The internal I/O area is used
for peripheral modules inside
the CPU; the external I/O area
is used for peripheral modules
outside the CPU.
For more information, refer to
the H8/510 hardware manual
and peripheral device
specification.
00FE80h
00FF80h
00FFA0h
00FFB0h
00FFB4h
00FFB8h
00FFBCh
00FFC0h
00FFD0h
00FFE0h
00FFF0h
00FFFFh
Internal I/O area
MPCCS
MCR1Z
MCR2Z
OPCCS2
OPCCS1
T/PZ
Not used
OPTCSZ
Expanded MPC
(not used)
PRNZ (not used)
CPCSZ (not used)
TPRCI (not used)
* CPCSZ is the CPC select for
the Centronics Interface.
* MPCCS and expanded MPC
signals are base signals for
MPCA8 internal register
decode. There is no external
signal.
* MCR1Z and MCR2Z are chip
select signals for the magnet
card reader.
(Using the lower 2bytes. )
* T/PZ is the internal decode
signal for USART built in
MPCA8. Thereis no external
signal. (Using the lower 2bytes.)
* OPCCS1 and OPCCS2
signals are decoded inside
the OPC (OPTION PERIP-
HERAL CONTROLLER)
using the option decode
signal OPTCS. There is no
external signal.
200000h
(MAX4MB)
FROS1
5FFFFF
* Lower 64KB of the ROS1 is
mapped on the 0 page area.
* ROS1 is decoded by
MPCA8.
600000h
BFFFFFh
800000h
A00000h
D00000h
RASPN1
VRAM
(2MB)
RASPN2
(2MB)
(1MB)
* The decode signals in the
area in the figure are supported
by MPCA8.
* RAS1 signals from MPCA8
correspond to 2MB 600000h to
7FFFFFh.
* OPTION RAM board
(2MB) interfaces using the RAS2
as the base signal.
* The actual VRAM is 512KB,
but it is accessed by every
128KB bank according to
VGAC specification.