UP-3301US
CIRCUIT DESCRIPTION
– 56 –
2-6. ISP2032
This IC has been developed specifically for the UP-3301 to achieve the
VGA CHIP and PSRAM interfaces.
Pin descriotion
3. Address map
3-1. Total memory space
The address map of the total memory space is shown below. The mem-
ory space is divided into the following blocks:
• 0page area (including the I/O area)
• VRAM
• RAM
• ROM
• Extended I/O area
Fig. 2
Pin
No.
Name
I/O
Function
1
/VMEM
In
VIDEO MEMORY DECODE
00000H ~ C1FFFFH
16bit/8bit access, 8 bit read from the CPU is
treated as 16-bit on the VGA.
2
/VMEM2
In
VIDEO MEMORY DECODE (ONLY FOR
GRAPHICS MODE; 8BIT)
C80000H ~ C9FFFFH 8-bit access only.
/VMEM and /VMEM2 differ in their apparent
address to each other, but the contents of
memory to be accessed are the same.
They differ in access method (WORD/BYTE).
3
/HWR
In
HIGH BYTE WRITE FROM CPU
4
/LWR
In
LOW BYTE WRITE FROM CPU
5
PHAI
In
CLOCK FROM CPU
6
VCC
7
/ISPEN
In
for ISP (In System Program)
8
/VWAITI
In
WAIT FROM VGA CHIP (IOCHRDY)
9
/VWAIT
Out WAIT TO MPCA
There are the following ORs.
1
IOCHRDY from VGA CHIP
2
1 WAIT is generated when VRAM. VGA I/
O is accessed. (Because IOCHRDY is
slow, 1 WAIT is generated prior to it.)
10
/DWRI
In
DELAYED WRITE (FOR VGA CHIP TIMING)
11
/DWRO
Out WRITE FOR /DWRI
12
/DRDI
In
DELAYED READ (FOR VGA CHIP TIMING)
13
/DRD
Out READ FOR /PRDI
14
RES
Out RESET OUTPUT
RESET
1
NOT (/RESET)
15
/RES
In
/RESET INPUT
16
A0
In
A0
17
GND
18
A20
In
A20
19
PCE21E
Out EXTENDED PSRAM1 DECODER (EVEN)
800000H ~ 8FFFFFH
20
PCE210
Out EXTENDED PSRAM1 DECODER (ODD)
800000H ~ 8FFFFFH
21
PCE220
Out EXTENDED PSRAM2 DECODER (ODD)
900000H ~ 9FFFFFH
22
PCE22E
Out EXTENDED PSRAM2 DECODER (EVEN)
900000H ~ 9FFFFFH
23
/IPLON0
In
IPL SIGNAL
24
/PSRF0
Out PSRAM REFRESH
25
/OWR
Out PSRAM WRITE (ODD SIDE)
26
/M3SWP
Out MODE3 BUS SWAP (FOR PSRAM ACCESS
DURING IPL)
27
Y2/SCLK
ISP
28
VCC
29
Y1/RESET
ISP
30
MODE
ISP
31
RASPN2E
In
EXTENDED PSRAM2 DECODER
(FROM MPCA)
800000H ~ 9FFFFFH
32
RASPN2
In
EXTENDED PSRAM2 DECODER
(FROM MPCA)
800000H ~ 9FFFFFH
33
/RASPN12
In
PSRAM DECODER (FROM MPCA)
600000H ~ 9FFFFFH
34
/AS
In
/AS FROM CPU
35
/RD
In
/RD FROM CPU
36
/RFSH
In
/RFSH FROM CPU
37
/SMEMR
Out VIDEO MEMORY READ (TO VGA CHIP)
38
/SMEMW
Out VIDEO MEMORY WRITE (TO VGA CHIP)
39
GND
40
/COE0
Not used
41
/IORD
Out VGA IO READ (TO VGA CHIP)
42
/IOWR
Out VGA IO WRITE (TO VGA CHIP)
43
/SBHE
Out BUS HIGH ENABLE (TO VGA CHIP)
44
/VIO2
Out VGA IO CHIP SELECT
Pin
No.
Name
I/O
Function
000000h
0 page area
(64KB)
00FFFFh
200000h
600000h
800000h
C00000h
F00000h
FFFFFFh
Extended I/O area
(1MB)
(4MB)
(2MB)
Flash ROM area
(4MB
STD RAM area
Extended RAM area
(2MB)
)
V-RAM area
(1MB)
EPROM area
D00000h
The lower 64 KB or less of the
Flash ROM area is mapped in
the 0PAGE area. By mapping
the ROM, it is possible to
accommodate RESET and
VECTOR ADDRESS.
Expansion I/O area: Space for an I/O device which needs to be arranged
in space other than the 0PAGE area.
MPCA8 uses the addresses from FFFF00H to FFFFFFH for an address
specification register (BAR) for SSP.
The I/O register and printer buffer RAM and the TCP/IP dual port RAM
are also located here.
VIO# (LCDC I/O): F10000H - F1FFFFH (Not used)
PBRAM: F00000H - F0FFFFH
DPCS# (TCP/IP): F20000H - F3FFFFH
Used as VRAM area for LCDC.
VMEM2#: C80000H - 08FFFFH
(128KB)
VIO2#: CE0000H - CFFFFFH
*
Internal and external I/Os of the
CPU are, 8-bit and fixed to 3-
states.
16bit BUS
8bit BUS
2 states
3 states
Содержание UP-3301
Страница 91: ...UP 3301US PWB LAYOUT 89 CHAPTER 9 PWB LAYOUT 1 MAIN PWB A side ...
Страница 92: ...UP 3301US PWB LAYOUT 90 B side 8 CUSTOMER DISPLAY PWB ...
Страница 93: ...UP 3301US PWB LAYOUT 91 2 IR PWB 3 LCD PWB A Side B Side 4 INVERTER PWB A Side B Side ...
Страница 94: ...UP 3301US PWB LAYOUT 92 5 MOTHER PWB 6 N F PWB 7 TOUCH PANEL PWB ...
Страница 95: ...UP 3301US PWB LAYOUT 93 ...
Страница 111: ......
