Sharp ER-A750, Руководство по обслуживанию

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3) Pin description
Pin
No.
Symbol
Signal
name
In/
Out
Function
1 RF Nu — Nu
2 JF Nu — Nu
3 PCUT Nu — Nu
4 FCUT Nu — Nu
5 VF Nu — Nu
6 STAMP Nu — Nu
7 SLF Nu — Nu
8 SLRS Nu — Nu
9 SLPMTD Nu — Nu
10 RES RES Out Peripheral output reset
11 TRG Nu — Nu
12 TRG Nu — Nu
13 INT0 POFF In Power off signal input
14 INT1 KRQ In
Interrupt signal (Key
interrupt request)
15 HTS1 HTS Out 8 bit serial port output
16 SCK1 SCK Out Serial port shift clock output
17 STH1 STH In 8 bit serial port input
18 RASV RASV Out Chip select
19 Nu Nu — Nu
20 VCC VCC — +5V
21 VSS GND — GND
22 INTMCR INTMCR Out Interrupt signal (MCR)
23 VRESC VRESC In
Turns active when reset and
power down is met
24 SLTMG GND — GND
25 SLRST GND — GND
26 AS AS In Address strobe
27 RD RD In Read strobe
28 WR WR In Write strobe
29 PHAI # In (
φ
) System clock (9.83MHz)
30 SDT7 Nu — Nu
31 SDT6 Nu — Nu
32 SDT5 Nu — Nu
33 VSS GND — GND
34 SDT4 Nu — Nu
35 SDT3 Nu — Nu
36 SDT2 Nu — Nu
37 SDT1 Nu — Nu
38 D0 D0 I/O Data bus
39 D1 D1 I/O Data bus
40 D2 D2 I/O Data bus
41 D3 D3 I/O Data bus
42 VSS GND — GND
43 D4 D4 I/O Data bus
44 D5 D5 I/O Data bus
45 D6 D6 I/O Data bus
46 D7 D7 I/O Data bus
47 SSPRQ NMI Out SSP interrupt request to CPU
48 RESET RESET In MPCA reset
49 INT2 VCC — +5V
50 INT3 VCC — +5V
51 RXDI RXDI Out
8 bit serial port output to
CPU
52 TXDI TXDI In
8 bit serial port input from
CPU
Pin
No.
Symbol
Signal
name
In/
Out
Function
53 SCK1 SCK1 In
Serial port shift clock input
from CPU
54 IRQ0 IRQ0 Out Interrput request to CPU
55 A0 A0 In Address bus
56 A1 A1 In Address bus
57 A2 A2 In Address bus
58 A3 A3 In Address bus
59 A4 A4 In Address bus
60 A5 A5 In Address bus
61 VSS GND — GND
62 VCC VCC — +5V
63 A6 A6 In Address bus
64 A7 A7 In Address bus
65 A8 A8 In Address bus
66 A9 A9 In Address bus
67 A10 A10 In Address bus
68 A11 A11 In Address bus
69 A12 A12 In Address bus
70 A13 A13 In Address bus
71 A14 A14 In Address bus
72 A15 A15 In Address bus
73 A16 A16 In Address bus
74 A17 A17 In Address bus
75 A18 A18 In Address bus
76 A19 A19 In Address bus
77 A20 A20 In Address bus
78 A21 A21 In Address bus
79 A22 A22 In Address bus
80 LCDC LCDC Out LCDC chip select signal
81 A23 A23 In Address bus
82 TRGI GND In GND
83 PTMG Nu — Nu
84 PRST Nu — Nu
85 INT4 VCC — +5V
86 IPLON IPLON0 In To option connector
87 MD1 GND — GND
88 MD0 GND — GND
89 TEST VCC — +5V
90 MA15 MA15 Out Image address 15
91 MA18 Nu — Nu
92 MA19 Nu — Nu
93 RCVRDY1 MCRRDY1 In
94 RCVRDY2 MCRRDY2 In
95 RCO Nu — Nu
96 IRTX IRTX Out I/R output for LED
97 UASCK UASCK Out I/R serial data shift clock
98 UARX UARX Out I/R serial data for CPU
99 UATX UATX In I/R serial data from CPU
100 VCC VCC — +5V
101 VSS GND — GND
102 IRRX IRDA In I/R input from IR unit
103 RCI GND — GND
104 PHAI PHAI In System clock (7.3728MHz)
105 DAX2 PHAI In System clock (7.3728MHz)
106 MCR1 MCR1 Out
107 MCR2 MCR2 Out
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