Sharp ER-A750, Руководство по обслуживанию

Страница: 45 / 105

2-5. Z80 CPU
1) Features
The extensive instruction set contains 158 instructions, including the
8080A instruction set as a subset.
•
NMOS version for low cost high performance solutions, CMOS
version for high performance low power designs.
•
Z0840006 - 6.17 MHz
•
CMOS Z84C0006 - DC to 6.17 MHz, Z84C008 - DC to 8 MHz,
Z84C0010 - DC to 10 MHz, Z84C0020 - DC - 20 MHz
•
6 MHz version can be operated at 6.144 MHz clock.
•
The Z80 microprocessors and associated family of peripherals
can be linked by a vectored interrupt system. This system can be
daisy-chained to allow implementation of a priority interrupt
scheme.
•
Duplicate set of both general-purpose and flag registers.
•
Two sixteen-bit index registers.
•
Three modes of maskable interrupts:
Mode 0 — 8080A similar;
Mode 1 — Non-Z80 environment, location 38H;
Mode 2 — Z80 family peripherals, vectored interrupts.
•
On-chip dynamic memory refresh counter.
Figure 1. Pin functions
2) Pin configuration
44 pin Quad Flat Pack (QFP), Pin Assignments
(Only available for 84C00)
3) General description
The CPUs are fourth-generation enhanced microprocessors with ex-
ceptional computational power. They offer higher system throughput
and more efficient memory utilization than comparable second- and
third-generation microprocessors. The internal registers contain 208
bits of read/write memory that are accessible to the programmer.
These registers include two sets of six general-purpose registers
which may be used individually as either 8-bit registers or as 16-bit
register pairs. In addition, there are two sets of accumulator and flag
registers. A group of "Exchange" instructions makes either set of
main or alternate registers accessible to the programmer. The alter-
nate set allows operation in foreground-background mode or it may
be reserved for very fast interrupt response.
The CPU also contains a Stack Pointer, Program Counter, two index
registers, a Refresh register (counter), and an Interrupt register. The
CPU is easy to incorporate into a system since it requires only a
5V power source. All output signals are fully decoded and
timed to control standard memory or peripheral circuits; the CPU is
supported by an extensive family of peripheral controllers.
The internal block diagram (Figure 3) shows the primary functions of
the processors. Subsequent text provides more detail on the I/O
controller family, registers, instruction set, interrupts and daisy
chaining, and CPU timing.
Figure 3. Z80C CPU Block Diagram
DATA
BUS
ADDRESS
BUS
CPU
CONTROL
CPU
BUS
CONTROL
SYSTEM
CONTROL
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
D1
D2
D3
D4
D5
D6
D0
D7
M1
MREQ
IORQ
RD
WR
RFSH
HALT
WAIT
INT
NMI
RESET
BUSREQ
BUSACK
CLK
+5V
GND
Z8400
Z80 CPU
A4
A3
A2
A1
A0
GND
RFSH
M1
RESET
NC
A5
D3
D5
D6
+5V
D2
D7
D0
D1
NC
CLK
D4
1
11
33
23
22 12
34 44
Z80 CPU
INTERNAL DATA BUS ALU
REGISTER
ARRAY
ADDRESS
LOGIC AND
BUFFERS
16-BIT
ADDRESS BUS
8-BIT
DATA BUS
INSTRUCTION
REGISTER
DATA BUS
INTERFACE
INSTRUCTION
DECODER
CPU
TIMING
CPU
TIMING
CONTROL
+5V
GND
CLOCK
8 SYSTEMS
AND CPU
CONTROL
OUTPUTS
5 CPU
CONTROL
INPUTS
7 – 15